open-fpga-verilog-tutorial
open-fpga-verilog-tutorial copied to clipboard
Published
20 hours ago •
Obijuan
Obijuan
not includen .vh file in archive .v
Processing icestick (platform: lattice_ice40; board: icestick)
Verbose mode can be enabled via -v, --verbose option
yosys -p "synth_ice40 -blif .pioenvs\icestick\hardware.blif" -q src\countsec.v
ERROR: Can't open include file `divider.vh'!
*** [.pioenvs\icestick\hardware.blif] Error 1
================================= [ERROR] Took 1.72 seconds =================================
The terminal process terminated with exit code: 1
Terminal will be reused by tasks, press any key to close it.
