Juan Gonzalez-Gomez

The leg part has been already refactored. I am working in my fork. When every part is finished, printed and tested I will merge into zowi's master Leg parts has...

This is weird! It should work. I've been able to reproduce it. I will try to isolate the problem to understand what is going on. I will tell you my...

This is the minimal circuit for reproducing the bug:  Icestudio File: [bug-min.zip](https://github.com/FPGAwars/icestudio/files/4656002/bug-min.zip) The verification pass ok, but when sinthesizing this error show up:  This is the verilog code...

All right! I've found the problem! Icestudio by default assign a default value of 0, so in the first pass, yosys uses N = 0 and the $clog2(0) function fails,...

> A quick "understanding" question: The $clog2() function should work the same as the one that was written in the code (log2)? Yes. The $clog2() is the verilog system function...

@donnmphone , could you please try the latest wip? You can download it from here: https://downloads.icestudio.io/

Hi Laulin! I've invited you to the wiki team. Once the invitation is accepted, please check if you can edit the wiki page (I am not sure if I've set...

Could you please try it now? (If it still does not work I will try something different. I am still learning about github teams)

yes, we have the following google group: https://groups.google.com/g/fpga-wars-explorando-el-lado-libre Initially was only in Spanish but now you could write in English. You are very welcome to join and comment/discuss your ideas

Reopened. For implemeting vhdl it is necesary first to support it in the backend (apio). Icestudio is the graphical part. I will leave this issue open as a remainder