Digital-IDE

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"show netlist" option cannot show correctly when other module instantiation in top module

2

I defined 2 verilog modules, one for DFF and one for EXAMP, I instantiated the DFF module twice in the EXAMP module, but when I use the "show netlist" option...

Collect-diamond

"PRJ_STRUCTURE": "customer" crushed everything

1

Issue Type: Bug Extension Name: fpga-support Extension Version: 0.2.6 OS Version: WSL2 Ubuntu x64 20.04.5 VS Code version: 1.76.0 ``` ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2022.2 (lin64) Build 3671981...

StrideZhou

目前digitalIDE似乎不支持任意目录下的文件解析，请问未来可以实现全文件夹解析吗？

miilTgy

用MYHDL生成的VCD文件，用插件查看波形时有问题

1

[siming.zip](https://github.com/user-attachments/files/15858866/siming.zip)  文件在附件当中，用插件查看时，信号可以添加，但是时间刻度没有数据，均为NaN ns，请帮忙看下,谢谢

xzrsds123

cyrus28214