naming optimizations

[Nic30]

• Prefix for HCL objects needs to be specific so it is more easy to automatically update code after library updates
  • visually separation of normal Python objects and HCL
  • simplifies search in code

• [x] Names of signal, interface or component

  • Involves: BasicRtlSimProxy, RtlSignal, HwIO, HwModule
  • now it is not clear what the name actually means
    • .name -> ._name - logical name, name from user description
    • ._name -> ._hdlName - physical name, full name with resolved name collisions etc.

• [ ] Backward type reference of signals and constant

• type property name is too long ._dtype -> ._ht

• [ ] Split HConst and HVar classes (because of performance reasons)

def tv(signal):
    return signal._dtype.getConstCls()

class RtlSignalOps():
    def __invert__(self):
        return self.naryOp(AllOps.NOT, tv(self).__invert__)

# currently the const class contains code also for signal/variable operator
class BitsConst:
    def __invert__(self):
        if isinstance(self, HConst):
            return Bits3val.__invert__(self)
        else:
            ...

• [x] Bits -> HBits (act as an int but it is not named int to avoid things like float inheriting from int)
• [x] hwt.synthesizer.unit.Unit -> hwt.hModule.HwModule (Using module stem because it is more widely used)
  • [x] ._interfaces -> ._hwIOs
  • [x] ._subunits -> ._subHwModules
  • [x] ._params -> ._hwParams
  • [x] ._paramsShared() -> ._hwParamsShared()
• [x] Interface -> HwIO
• [x] Signal -> HwIOSignal (adding HwIO so user do not think that this is the signal instance which should be normally used for communication inside of module)
• [x] Param -> HwParam
• [x] HValue -> HConst (same convention as in LLVM)
• [x] Operator -> HOperatorNode
• [x] OpDefinition -> HOperatorNodeDef
• [x] AllOps -> HwtOps
• [x] UniqList -> SetList (same convention as in LLVM)
• [x] SimTestCase.u -> SimTestCase.dut (replacing u after Unit -> HModule)
• [x] EmptyUnit -> hwtLib.abstract.emptyHModule.EmptyHModule
• [x] hwt.synthesizer.utils -> hwt.synth
• [x] HsStructIntf -> HwIOStructVldRd
• [x] StructIntf -> HwIOStruct
• [x] VldSyncedStructIntf -> HwIOStructVld
• [x] RdSyncedStruct -> HwIOStructRd
• [x] HdlType_to_Interface -> HdlType_to_HwIO
• [x] Interface_to_HdlType -> HwIO_to_HdlType
• [x] DifferentialIntf -> HwIODifferentialSig
• [x] RegCntrl -> HwIORegCntrl
• [x] TristateSig -> HwIOTristateSig
• [x] UnionSink -> HwIOUnionSink
• [x] UnionSource -> HwIOUnionSource
• [x] RdSynced -> HwIODataRd
• [x] RdSync -> HwIORdSync
• [x] VldSynced -> HwIODataVld
• [x] VldSync -> HwIOVldSync
• [x] Handshaked -> HwIODataVldRd
• [x] HandshakeSync -> HwIOVldRdSync
• [x] Clk -> HwIOClk
• [x] Rst -> HwIORst
• [x] Rst_n -> HwIORst_n
• [x] ReqDoneSync -> HwIOReqDoneSync
• [x] BramPort_withoutClk -> HwIOBramPort_noClk
• [x] BramPort -> HwIOBramPort
• [x] FifoWriter -> HwIOFifoWriter
• [x] FifoReader -> HwIOFifoReader
• [x] AxiStream -> Axi4Stream
• [x] hwtLib.amba.axi_intf_common -> hwtLib.amba.axi_common
• [x] walkPhysInterfaces -> HwIO_walkSignals
• [x] walkFlatten -> HwIO_walkFlatten
• [x] packHwIO -> HwIO_pack
• [x] connectPacked -> HwIO_connectPacked
• [x] IntfIpMetaNotSpecified -> IntfIpMetaNotSpecifiedError

flatten to parent:

• move constants from hwt.synthesizer.rtlLevel.constants, hwt.hdl.constants to hwt.constants
• hwt.synthesizer.interfaceLevel.interfaceUtils
• hwt.synthesizer.rtlLevel.signalUtils
  • walkers -> rtlSignalWalkers
  • ops -> rtlSignalOps
• hwt.synthesizer.hObjList -> hwt.hObjList