Nic30

It seems that this functionality is connected with intensive code removal and refactoring, I will do it during weekend.

Now 8c519e4 the preprocessor exports correct file/line map for input string. This map is available in https://github.com/Nic30/hdlConvertor/blob/verilog_pp_line_directive/src/convertor.cpp#L139 verilog_pp::VerilogPreprocOutBuffer but it is not currently used. Next step is to use this...

https://github.com/SymbiFlow/sv-tests/pull/316

It may not be so easy as the python AST object are build in c++, but we may just need to wrap this method in GIL.

The one of formats used by Xilinx Vivado is IP-XACT (usually described using component.xml) from this it is possible to generate configured ip core (.xci file generated by vivado after...

Example files generated in ipcore folder [mem_axi_register_slice.zip](https://github.com/Nic30/hwt/files/5701597/mem_axi_register_slice.zip)

* config/declarations/implementations * circuit growth (Top down configuration bottom up RTL building) * Rules for in memory circuit modifications and introspection * IpPackaging and distribution * Vivado/Quartus integration

https://github.com/Nic30/jupyter_widget_hwt/tree/master/examples

* Update wiki about how to create a component/interface * How to actually see during the debugging https://github.com/Nic30/hwt/blob/master/hwt/simulator/utils.py#L8 * Development best practices, black boxes, code reuse, in team work parallelization,...

https://github.com/Nic30/jupyter_widget_hwt/tree/master/examples