Nic30

I could potentially hire someone or make thesis topic out of it. However I can not do it just because it would be nice. I need some company to explicitely...

@hs-apotell About construct identification for schematic: https://github.com/Nic30/hwtGraph/blob/master/hwtGraph/elk/fromHwt/statementRenderer.py After elaboration is somehow working I possibly can reuse some code for detection you require.

Hello, the feature is not completed yet. There is an information about origin of the line in preprocessor https://github.com/Nic30/hdlConvertor/blob/master/include/hdlConvertor/verilogPreproc/out_buffer.h#L32 But it is not propagated to HDL AST. It is easy...

As @Thomasb81 mentioned content of include file may not be Verilog code. But there is yet an another problem. The actual file name and file name which can be overriden...

Include directive can be almost everywhere that is why the included file can contain only fragment of the code (e.g. an array initialization) which is not a valid verilog because...

@hs-apotell , True. The filename is required to resolve actual position in code. But there is another problem. The preprocessor takes the code from the files and generates new string...

#134

Hello, do you need only parsing and export of BLIF or do you also need to convert arbitrary Verilog/VHDL to BLIF and back? BLIF is a simple format, It is...

It really seems that BLIF is so trivial that there is no need to use any lexer/parser generator. If I understand correctly things like Yosys can work with BLIF. Can...

_I just looking at summary in your resume and if I replace university name it is basically same as mine._ FSM detection and boolean function optimization is well studied topic,...