[None] [feat] reduce add fusion

[zongfeijing]

Summary by CodeRabbit

• New Features

  • Added GPU-accelerated reduce-add operation supporting half-precision (fp16) and bfloat16 data types for efficient tensor operations with residual addition and configurable reduction parameters.

• Tests

  • Added comprehensive tests for the reduce-add operation including correctness validation against PyTorch references and performance benchmarking across multiple configurations.

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Description

Test Coverage

PR Checklist

Please review the following before submitting your PR:

• PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.

• PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

• Test cases are provided for new code paths (see test instructions)

• Any new dependencies have been scanned for license and vulnerabilities

• CODEOWNERS updated if ownership changes

• Documentation updated as needed

• Update tava architecture diagram if there is a significant design change in PR.

• The reviewers assigned automatically/manually are appropriate for the PR.

• [ ] Please check this after reviewing the above items as appropriate for this PR.

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[coderabbitai[bot]]

📝 Walkthrough

Walkthrough

Introduces a CUDA-based reduce-add kernel module with type-generic support for fp16 and bf16, compile-time TOPK unrolling, and runtime dispatch based on topk values (2, 4, 6, 8, 16). Includes PyTorch operator binding and comprehensive test coverage with correctness and benchmark tests.

Changes

Cohort / File(s)	Summary
CUDA Kernel Implementation cpp/tensorrt_llm/kernels/reduceAddKernel.cu	New persistent CUDA kernel with TypeTraits specializations for half and __nv_bfloat16, vectorized 128-bit add operations, FP32 accumulation, and type conversions. Includes runtime dispatch function launchReduceAddKernel selecting template instantiations based on topk value, and helper functions for SM count caching and grid sizing.
Kernel API Header cpp/tensorrt_llm/kernels/reduceAddKernel.h	New header declaring template function invokeReduceAdd<T> for public API surface with specializations for half and __nv_bfloat16.
Build Configuration cpp/tensorrt_llm/thop/CMakeLists.txt	Added reduceAddOp.cpp to th_common SHARED library source list.
PyTorch Binding cpp/tensorrt_llm/thop/reduceAddOp.cpp	New PyTorch extension exposing CUDA kernel via torch_ext::reduceAdd function with input validation, dtype support (fp16, bf16), and operator registration under trtllm namespace.
Test Suite tests/unittest/_torch/thop/parallel/test_reduce_add.py	New test module with parametric correctness tests across multiple configurations and dtypes, plus benchmark test comparing custom kernel against PyTorch reference with 1.5x performance assertion.

Sequence Diagram

sequenceDiagram
    participant PT as PyTorch<br/>(Python)
    participant Bind as PyTorch Binding<br/>(C++)
    participant Dispatch as Runtime Dispatch<br/>(launchReduceAddKernel)
    participant Kernel as CUDA Kernel<br/>(reduceAddKernel)
    participant GPU as GPU Memory
    
    PT->>Bind: torch.ops.trtllm.reduce_add(input, residual)
    Bind->>Bind: Validate shapes, dtypes, contiguity
    Bind->>Bind: Allocate output tensor
    Bind->>Dispatch: launchReduceAddKernel<T>(input, residual, output, topk, ...)
    Dispatch->>Dispatch: Select instantiation based on topk value
    Dispatch->>Kernel: Launch reduceAddKernel<T, TOPK, VEC_SIZE>
    Kernel->>GPU: Load 128-bit vectors from input
    Kernel->>GPU: Accumulate in FP32
    Kernel->>GPU: Convert back to T, add residual
    Kernel->>GPU: Store output
    Kernel-->>Dispatch: Kernel completion
    Dispatch-->>Bind: Return
    Bind-->>PT: Return output tensor

Estimated code review effort

🎯 4 (Complex) | ⏱️ ~45 minutes

• cpp/tensorrt_llm/kernels/reduceAddKernel.cu: High complexity due to template metaprogramming, TypeTraits specializations for multiple types, vectorized memory operations, FP32 accumulation logic with type conversions, and runtime-to-compile-time dispatch mechanism. Dense CUDA-specific optimizations require careful verification of correctness.
• Type conversion correctness: Multiple paths for converting between FP32 and FP16/BF16 with residual handling—requires careful review to ensure numerical stability and proper rounding.
• PyTorch binding layer (reduceAddOp.cpp): Input validation logic and dtype routing; moderate complexity but depends on correct kernel interface.
• Test coverage: Parametric and benchmark tests are well-structured but require understanding of expected behavior across configurations.

Pre-merge checks and finishing touches

❌ Failed checks (2 warnings)

Check name	Status	Explanation	Resolution
Description check	⚠️ Warning	The PR description is almost entirely empty template boilerplate with no filled-in sections for Description, Test Coverage, or PR Checklist items - critical context about the feature implementation, rationale, and testing strategy is completely missing.	Fill in the Description section with what reduce-add fusion does and why it's needed, complete the Test Coverage section listing the test files (test_reduce_add.py), and check off relevant PR Checklist items.
Docstring Coverage	⚠️ Warning	Docstring coverage is 25.00% which is insufficient. The required threshold is 80.00%.	You can run @coderabbitai generate docstrings to improve docstring coverage.

✅ Passed checks (1 passed)

Check name	Status	Explanation
Title check	✅ Passed	The title '[None] [feat] reduce add fusion' clearly describes the main feature being added - a reduce add fusion operation - which aligns with the code changes introducing new CUDA kernels and PyTorch bindings for reduce-add functionality.

✨ Finishing touches

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🧪 Generate unit tests (beta)

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