Hybrid Data x Context Parallelism Feature

[parthmannan]

What does this PR do ?

Added PR for main here - https://github.com/NVIDIA/Megatron-LM/pull/2282

Design document discussed in MCore sync meeting - https://docs.google.com/document/d/1MnIPQ_VbpDNp-adtvcEv-SYx6A8rtt3-fDdxbcdrmk0/edit?usp=sharing

The first issue this MR is trying to solve is the imbalance between DP ranks when using packed sequences (for example in SFT). While packing sequences can help reduce variability in total sequence length, it does not guarantee equal workload. Attention compute is quadratic to sequence length and a single long sequence of 1k has 2x more compute than a packed sequence made of 2x512 length. This problem gets much worse when we have very large sequences and/or a large variation between sequence lengths. This MR schedules a variable number of microbatches per rank in DPxCP group to ensure balanced workload.

The second issue this MR is trying to solve is redundant CP communication. Our context parallel size is based on the full packed sequence length (usually the max seq length of all samples). For example, if a sequence of 1k requires CP2, we apply CP2 to a packed sequence of 2x512 as well. But in reality, we can easily partition the packed sequence of 2x512 into 2 GPUs by separating the 2 samples without any CP. This MR introduces dynamic context parallelism where each sample is individually scheduled with a dynamic CP group.

To achieve the above, we introduce a balanced scheduler and a dataloader wrapper. The dataloader wrapper is responsible for collecting the metadata which informs the scheduler of the sequence length of each sample across the entire global batch. This dataloader breaks up the packed sequences into individual samples as they are individually scheduled. Once we have the metadata, we can perform the scheduling using the balanced scheduler which assigns samples to ranks (across DPxCP group) and a dynamic CP group size. To avoid any deadlocks, we divide the schedule into groups (this replaces the notion of microbatches). Within each group, each rank is part of a fixed CP group. However, each rank may run different number of samples in order for all ranks to have a balanced compute.

We have run performance and correctness evaluations using the feature. Using the SFT packed dataset with max seq len of 128k and testing with LLaMa3 8B dummy model, we see 3x performance improvement with this feature. While there is room for improving the baseline itself, the speedup should remain in the 2-3x range.

This is how 128k seq len with CP16 looks like (without this feature). The GPU is bound by CP communications.

This is how 128k seq len with CP16 looks like (with this feature). The GPU is bound by attention compute since all redundant comms have been removed.

Feature correctness (@xiaoyao0115)

This is the first milestone of this feature and there's many improvements that we want to make in the future releases.

1. The feature does not support pipeline parallelism or FSDP yet. We hope to add PP support next.
2. The feature is limited to creating dynamic groups of CP of power 2. We hope to add complete dynamic support using changes in TransformerEngine DPA.
3. The feature does not support CUDA graphs.
4. The feature works best with FlashAttention instead of cuDNN FusedAttention. This is because the changing lengths and CP size make cuDNN recompile the graph and all performance gains are lost. We'll advocate for dynamic support to cuDNN FusedAttention.

Contribution process

flowchart LR
    A[Pre-checks] --> B[PR Tests]
    subgraph Code Review/Approval
        C1[Expert Review] --> C2[Final Review]
    end
    B --> C1
    C2 --> D[Merge]

Pre-checks

• [ ] I want this PR in a versioned release and have added the appropriate Milestone (e.g., Core 0.8)
• [ ] I have added relevant unit tests
• [ ] I have added relevant functional tests
• [ ] I have added proper typing to my code Typing guidelines
• [ ] I have added relevant documentation
• [ ] I have run the autoformatter.sh on my PR

Code review

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[copy-pr-bot[bot]]

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[yanring]

Hi @parthmannan, could you also start a main PR?

[parthmannan]

Hi @parthmannan, could you also start a main PR?

Added PR for main here - https://github.com/NVIDIA/Megatron-LM/pull/2282 Will resolve conflicts shortly.

[kunlunl]

/ok to test aa3858d

[kunlunl]

/ok to test 60234b3

[parthmannan]

/ok to test https://github.com/NVIDIA/Megatron-LM/pull/2054/commits/e2a32cb54edf51e9cb000b7e8ab4b55e58e7d846

[parthmannan]

/ok to test https://github.com/NVIDIA/Megatron-LM/pull/2054/commits/d53c323bcfb6f088de4ad919adeccf615737f75a

[kunlunl]

/ok to test e2a11bb

[copy-pr-bot[bot]]

/ok to test e2a11bb

@kunlunl, there was an error processing your request: E2

See the following link for more information: https://docs.gha-runners.nvidia.com/cpr/e/2/

[kunlunl]

/ok to test d53c323bcfb6f088de4ad919adeccf615737f75a

[parthmannan]

/ok to test https://github.com/NVIDIA/Megatron-LM/pull/2054/commits/70b9758cefdf016eb30559693f9dfc6ad4a8e246

[parthmannan]

/ok to test https://github.com/NVIDIA/Megatron-LM/pull/2054/commits/9387269bf9a641293cbccd68bbbe4f1db874453d

[parthmannan]

/ok to test https://github.com/NVIDIA/Megatron-LM/pull/2054/commits/2bde6c85a99988ad4c3a9d37e633908dfb3e8323

[parthmannan]

/ok to test https://github.com/NVIDIA/Megatron-LM/pull/2054/commits/604ddd207fddb3f53adffb3e1190d94789a6e8b3