Consider taping out a test accelerator for no cost using open source tooling + PDK

[mithro]

Thanks to the funded provided by DARPA there is an increasingly capable, fully automated, RTL to GDS toolchain for creation ASICs called OpenROAD (https://theopenroadproject.org/). To help support the project, Google has partnered with SkyWater to release a fully open source, manufacturable 130nm PDK (https://github.com/google/skywater-pdk) and with efabless a run a regular no-cost MPW program for open source designs (https://efabless.com/).

It would be awesome to see a test accelerator created and taped out in this process! It could also become an excellent benchmark.

Some other interesting links;

• https://j.mp/op22-gtools
• http://cfu-playground.rtfd.io/
• https://www.youtube.com/c/ZeroToASIC/videos
• https://www.youtube.com/watch?v=EczW2IWdnOM
• https://www.youtube.com/watch?v=lq2BpWwcyQM

[shtaxxx]

Thank you very much for interesting proposal. Using NNgen, we can generate a model-specific RTL design, which means we cannot change the model structure after we synthesize the RTL design. So the NNgen-based ASIC will be a specialized chip for a specific model. It might be still useful as the feature extractor of the following output layers.