Moritz Schneider

I do not understand your issue. Just follow the steps in the [verif readme](https://github.com/openhwgroup/cva6/blob/master/verif/README.md): > These commands will install the riscv gcc 13.1.0 compiler which is the latest version. Once...

Hi, Thanks for the report. I believe you are correct. Would you mind fixing this and posting your first PR? I believe the fix should just change this line to...

> Hello @Moschn You speak about a PMP benchmark. Where is this test/benchmark ? Hi @JeanRochCoulon, with PMP benchmark I mean this: https://github.com/riscv-software-src/riscv-tests/blob/master/benchmarks/pmp/pmp.c

This is expected behavior. CVA6 does not support low granularity for PMP, and NA4 is the lowest granularity. Spike on the other hand supports all granularities. Actually, the RISC-V privilege...

Oh, sorry for that, I did not read your issue thoroughly enough. I found the regression and proposed a fix in #2469.

Take a look at [core/Flist.cva6](https://github.com/openhwgroup/cva6/blob/0c60bc6e3dccd61753aeb2176fc1d586b283578b/core/Flist.cva6). It should contain most files required for synthesis. You can also check the Makefile for more details.

Just adding the files will not work, as you will have to define some parameters and extra files/IP. We do not currently have a readme how to create a vivado...

Our setup is not done in the Vivado block design. I also don't think it is easy to convert our design/IPs to Vivados block design. So I believe you probably...

Openpiton instructions are different and I do not know if they apply to our FPGA image. I believe the instructions in CVA6-sdk should work. If you want to use openpiton...

A crossbar is just a simplified interconnect where every master is connected to every slave. You will need some basic knowledge of system-verilog to connect things to the interconnect. I...