I write few codes about FEMU ZNS controller-mapping, multi-channel and multi-way latency emulation

[inhoinno]

Hello, thanks for this emulator. Considering the contribution of FEMU, it means a lot I saw there is no emulation for zns ssd, so I wrote some codes for this

• Controller level Zone-Channel mapping (I call it Zone-Channel associativity)
• Multi-channel and Multi-way physical page mapping
• and zns latency emulation without dedicated qemu thread

About emulating ZNS SSD time, I refer to the latency model inside of BBSSD and OCSSD About Zone-Channel mapping, I mapped ppa w.r.t channel first, and then mapped ppa w.r.t ways (e.g. ZNS 1-to-1 ppa goes like : 0 4 8 12(for zone0) and ZNS 1-to-All ppa goes like : 0 1 2 3(for zone 0), when ZNS SSD with 4chnl) for mapping, I guess there is many available methods.

and you can configure max channel, associativity, ways like bbssd manner

//zns.c:1503
static void znsssd_init_params(FemuCtrl * n, struct zns_ssdparams *spp){
    spp->pg_rd_lat = NAND_READ_LATENCY;
    spp->pg_wr_lat = NAND_PROG_LATENCY;
    spp->blk_er_lat = NAND_ERASE_LATENCY;
    spp->ch_xfer_lat = NAND_PROG_LATENCY/4;
    /**
     * @brief Inhoinno : To show difference between 1-to-1 mapping, and 1-to-N mapping,
     * at least one param among these four should be configured in zns ssd.
     * 1. SSD size  2. zone size 3. # of chnls 4. # of chnls per zone
    */
    spp->nchnls         = 32;           
    spp->zones          = n->num_zones; 
    spp->chnls_per_zone = 8;
    spp->ways           = 4;
    
    /* TO REAL STORAGE SIZE */
    spp->csze_pages     = (((int64_t)n->memsz) * 1024 * 1024) / MIN_DISCARD_GRANULARITY / spp->nchnls / spp->ways;
    spp->nchips         = (((int64_t)n->memsz) * 1024 * 1024) / MIN_DISCARD_GRANULARITY / spp->csze_pages;
}

I evaluate this extension by fio bench briefly, all results are set to 4way you can see raw data and jobfile here : https://github.com/inhoinno/femufio/tree/master/zns_ex about the performance, this is a single register model, so performance might not seem doubled
However, I'm sure that the latency model can be easily adapted to the double register model.

Thanks, again

[huaicheng]

Thanks for the patch! This can be a nice addition to FEMU.

Do you mind squashing all the commits into one and cleaning the code changes a little bit before I can merge it? I noticed your commits included many debugging statements and changes to files not related to ZNS functionality. We can target ZNS zone mapping and latency emulation for this patch and leave the rest for the future.

[inhoinno]

Thanks for the patch! This can be a nice addition to FEMU.

Do you mind squashing all the commits into one and cleaning the code changes a little bit before I can merge it? I noticed your commits included many debugging statements and changes to files not related to ZNS functionality. We can target ZNS zone mapping and latency emulation for this patch and leave the rest for the future.

I'll get right on it

[huaicheng]

I will port your ZNS-related changes in another commit and discard changes to non-ZNS files. Thanks for the patch!