Michael J. Baars

> I have made an [attempt at such notes](https://github.com/mwrnd/notes/tree/main/XDMA_Communication) Thanks! :) Cool. Doesn't look like Xilinx/AMD is doing anything with the pull requests though :(

> I have made an [attempt at such notes](https://github.com/mwrnd/notes/tree/main/XDMA_Communication). Hi Matthew, I see that it provides a README.md file in the 'Markdown' plain-text file format. It looks best when pasting...

There is no Address Editor when opening the [AXI4 Memory Mapped Default Example Design](https://docs.xilinx.com/r/en-US/pg195-pcie-dma/AXI4-Memory-Mapped-Default-Example-Design) from a DMA/Bridge Subsystem for PCI Express added through the IP Catalog, because there is no...

> The example designs are not easily altered. They exist to prove functionality. Well, this example design does not function very well with the scripts provided. Even with the BRAM...

Matthew, > Do not edit the Block Memory Generator. That's exactly where to edit the BRAM size! I was at exactly the right spot! ``` ===>./io.sh xdma0, channel 0:0, block...

> When you edit the Range (Memory Size) in the [Address Editor](https://docs.xilinx.com/r/en-US/ug994-vivado-ip-subsystems/Addressing-for-Block-Designs) and leave the Block Memory Generator on Auto that value (Address Width) will be propagated throughout the project....

Matthew, I've tried a script like yours, and I noticed two things while testing different IP Customizations: ``` PW PD 18K 36K AW 0) 256 8192 0 64 13 ->...

About my first item: Thanks for your elaborate answer, but: > Refer to the [Block Memory Generator Product Guide Pg#90, _Block RAM Usage_](https://docs.xilinx.com/v/u/en-US/pg058-blk-mem-gen). `256/72~=3.5556~=4`. Some of the BRAM is lost...

Hi Matthew :) Once again, thank you for your elaborate response. We learn as we go. > Vivado will not let you directly connect two busses with different data widths...

> I'll be continuing to [Section 4.2: Tandem Configuration](https://docs.opalkelly.com/xem8310/brk8310-breakout-board/pci-express-reference-design/) now. [PG195 DMA/Bridge Subsystem for PCI Express (4.1), Tandem Configuration or Dynamic Function eXchange breaks Open IP Example Design.](https://support.xilinx.com/s/question/0D54U000080lSg5SAE/pg195-dmabridge-subsystem-for-pci-express-41-tandem-configuration-or-dynamic-function-exchange-breaks-open-ip-example-design?language=en_US)