Mike Thompson

> In the 40s dir (and rvfi agent) we have a lot of "support logic" which we use in formal. ... the "logic" of it should be in a file...

> Say one needs rs1 of an instruction word, then one's assertion module doesn't need to create new signals and do all the [19:15] stuff itself, it could just refer...

> I think an instruction bus-monitor and a disassembler should be kept separately; Agreed. This requires us to have alignment on the definition of the data structure that represents an...

Hi @MarioOpenHWGroup. This PR now has a couple of conflicts. Can you resolve these? Thanks!

> I couldn't get it to work. (Not sure why, because the LRM grammar seems to say it is okay, but Xcelium thought otherwise.) Can you expand on this @silabs-robin?...

Hi @Nicolas-Gaudin, thanks for your interest in CORE-V-VERIF. We do not use Verilator as a sign-off simulator, so Verilator has "best effort" support. Having said that, the interrupt test is...

Hi @szbieg, this is a clever idea. Some things to consider: 1. The repos that are cloned by the CORE-V-VERIF Makefiles are not intended to be used to submit updates...

> My use case was an automation of workspace preparation. It is not clear what that means. When the Makefiles clone the RTL, riscvdv and svlib repositories it is assumed...

Hi @yesilzeytin, thanks for your issue. The `/release` branches on core-v-verif are intended for internal use only. They are used as "staging branches" from `/dev` to/from the `master` branch. I...

Hi @guojiazhuxi, thanks for your issue. AFAIK, currently there are no OpenHW members using VCS for CV32E40P in CORE-V-VERIF, so the Makefiles have suffered from "bit rot". We try to...