Mike Thompson

icon indicating a website link http://www.openhwgroup.org icon indicating an email [email protected]

icon company @openhwgroup icon location Ottawa, Ontario, Canada icon location Functional verification of RTL for ASICs and FPGAs. Sole Proprietor at Covrado and Director of Engineering, Verification Task Group at the OpenHW Group.

Results 442 comments of Mike Thompson

[TASK] Integration with latest Kernel from FreeRTOS.org

@jquevremont, @anjaliigedam, what is the status of this issue?

[TASK] Feature to transform cache ways into a scratchpad

> Features to be presented on Feb. 4th meeting. @jquevremont @TulikaSi, what is the status of this issue?

[TASK] Feature to transform cache ways into a scratchpad

@jquevremont @TulikaSi, what is the status of this issue? Was it presented, and did we reach a conclusion?

work-ver/Variane_testharness Fail!

Hi @FranDuqueAyachi, I _think_ your issue is resolved, so I am closing this issue. Feel free to open a new issue if need be. Thanks!

[Bug Report] implict address truncation

Hi @zarubaf, what is the resolution of this issue? It _looks_ like it will be `WontFix`. Please confirm.

Failure to detect cache coherency violation.

Thanks for your insights @Phantom1003. @zarubaf, please have a look at this an confirm whether or not this issue is a real bug. Thanks!

[TASK] Integration with CORE-V-FreeRTOS

@jquevremont, @anjaliigedam, what is the status of this issue?

[TASK] Integrate Linux Boot on FPGA to Thales-CI Verification

@jquevremont, @sjthales, @Gchauvon, what is the status of this issue?

error during make verilate

Hi @hhhsiang > Besides, I found that there is no "share" folder under $RISCV/riscv64-unknown-elf/ What was the command you used to generate `work-ver/Variane_testharness rv64um-v-divuw`? It looks to me like you've...

error during make verilate

Hmmm. This looks like a duplicate of #730. I will close this one and we can track progress on that issue.