Mike Thompson

Thanks for this @olofk. I like your suggestion so much that I have taken the liberty of assigning this issue back to myself. @all, I won't be able to investigate...

Done. Verible wanted to make a lot of changes to both bhv and rtl files. I only pushed in the verible-ized versions of the files modified in this pull-request, namely...

Ha! I resubmitted using `verible-verilog-format` version `v0.0-1149-g7eae750` and it seems to work.

There hasn't been any new discussion on MM on this topic since 2020-06-16 and I think this issue can be quickly resolved by updating the Makefile in example_tb to use...

Hi @strichmo, if I merge in [core-v-verif pr #287](https://github.com/openhwgroup/core-v-verif/pull/287) will it impact the Designer's ability to reproduce this error?

Hi @Suxiaojie-iot, the items you mention are deliberate changes, not problems. Please refer to the [cv32e40p user manual](https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40p_um/en/latest/index.html). Also, in the future, please do not mix multiple topics in a...

The `core` testbench and `uvmt_cv32` verification environment in [core-v-verif](https://github.com/openhwgroup/core-v-verif) both use the **_cv32e40p_manifest.flist_** to compile the core, but the Makefile in the example_tb does not.

Hi @Silabs-ArjanB, @davideschiavone, I have removed the `Type:Enhancement` label as I am unconfortable waiving this issue for RTL freeze. There is a chance, however slight, that users of the example_tb...

The "flist" format is a quasi-standard file format supported by all SV simulators (although I do not know if that includes Verilator). So, for example, `xrun -f manifest_file` compiles all...

@davideschiavone, @Silabs-ArjanB, I am not sure why this issue was closed. Very few of the goals defined above have been met.