SPMC_Queue
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Confusion about using alignas(128)
struct alignas(64) Block
{
uint32_t idx = 0;
T data;
} blks[CNT];
alignas(128) uint32_t write_idx = 0;
I'm wondering why alignas(128) is used here instead of alignas(64) or anything.
Each block takes up one or more cachelines, and write_idx occupies a cacheline afterwards. Is there any reason to ensure write_idx must be aligned as 128 bytes instead of 64?
While CNT satisfies the constraint "CNT must be power of 2", I suppose there is no difference between the effect of alignas(64) and alignas(128) here as write_idx will always fall on the 128 boundaries.
I'm still new to low level programming, not sure if I understand things correctly.