Manar

The verilog parser doesn't support the dot operator in the module header

1

In the attached example, the parser can't process the `.mem({ \mem[0][0] , \mem[0][1] , \mem[1][0] , \mem[1][1] })` in the module header. Iverilog compiles the verilog file without flagging any...

PDN Question: How to handle multiple power domain connections ?

10

In this design, we have a macro `user_proj_example` which has four power domains: `vccd1` `vccd2` `vdda1` `vdda2`. The issue we are having is that pdngen shorts all the power domains...

Invalid verilog syntax at sky130_fd_sc_hd__lpflow_bleeder.functional.v

1

## Expected Behavior The `endif` directive should be followed by the macro name commented out. Correct behavior is like `endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V` where the macro the name is commented out...

Invalid verilog syntax at sky130_fd_sc_hd__dlxbn.behavioral.pp.v and sky130_fd_sc_hd__dlxbn.behavioral.v

3

## Expected Behavior Verilog views shouldn't have any syntax errors. ## Actual Behavior The behavioral model for the `sky130_fd_sc_hd__dlxbn` has an invalid verilog syntax at `wire 1;` The issue exists...

Netgen isn't case sensitive

4

In the attached test case, the design has two ports with the same name but one is uppercase and the other is lower case. Netgen reports one pin mismatch because...