NeoPixelBus
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Makuna
ESP32 I2s Parallel support alternate cadence to reduce DMA memory usage
Is your feature request related to a problem? Please describe. DMA memory is a scarce resource; and with the parallel methods are even worse since x8 or x16 channels is allocated even if the sketch only uses two or three.
Describe the solution you'd like Support a 3 step cadence option for i2s parallel.
Additional context Today the 4 step cadence is used (1/4,3/4 pulse ratio). This aligns memory and makes memory access faster at the cost of extra memory (4 x per byte to send). The new ESP32 S3 LCD uses a 3 step cadence (1/3, 2/3 pulse ratio). This uses 25% less memory, but at a cost of memory updates. RP2040 parallel demonstrates the ability to expose the option for 3 step or 4 step for sketch author.
