MIPT-ILab
Implement Data Cache Unit and introduce it into the pipeline
We have a cache model implemented, but it is not connected to PerfSim.
AMB: Data Cache Unit is implemented and performance studies are made on memory stress trace.
On cache hit, pipeline operates as usual
On cache miss, pipeline is stalled. Address of missed line is pushed to a long-latency port which is monitored by separate method (clock_cache). When data is returned, it is filled into cache so pipeline is unstalled.
@trexxet I assigned you to severing tasks that you may complete during summer. They are 20 points, covering all requirements for 1st and 2nd term.
@pavelkryukov I apologize for the delay. I didn't check e-mail due to exams. I'll take on these tasks right after exams (approximately 22-25 Jun), and I'm sure I'll complete them by the end of summer. However, I need to examine each problem to estimate time to complete them, so I'd like to do it after exams. I hope this wouldn't delay any work on project.
@pavelkryukov Sorry, I had to retake one of the exams recently.
I think I'll begin with #290 and #354. They are rather simple and would let me understand current project's structure better. They are going to take 1 week if everything is okay, max 2 weeks. Then I'll switch to syscalls (#122 and #304), I expect that these tasks can be done in 2 weeks. After that I will do #17 (this), #18 (which I'm not assigned to yet), and #269. They require some study, and I estimate the time to do them in 2-3 weeks.
So, after completing #290 and #354 I'll inform you about my deadlines for other tasks. Is this okay?
Ok.
I think I'll begin with #290
Not sure it is a very simple thing, as it requires some deep dive into GDB internals.
What do you mean by #18? It is completed already IMO.
As I see, for #18 some research should be finished to explain logarithmic law.