Verify correctness of read-after-write behavior

[pavelkryukov]

Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are jalr and instruction operating with CSRs:

https://github.com/riscv/riscv-tests/pull/258 https://github.com/riscv/riscv-tests/pull/263

Your objective is to convert these test cases to unit tests, similarly to tests we have already:

https://github.com/MIPT-ILab/mipt-mips/blob/081acc60940fd3f6181dc8888045b3ca7319d61b/simulator/risc_v/t/unit_test.cpp#L80-L88

After test implementation, you might have to fix our implementation of instructions in alu.h. After that, you may build and run test binaries from trackers mentioned above.