Alexander Meißner

It is already buried in the depths of this conversation: > ARMv8 AArch64: It has almost double the registers (31) that x86-64 (16) and BPF (11) have. The reason for...

Do you have a representative body of BPF programs to analyze how much register pressure we currently have? Even then, future programs could change everything.

> The eBPF was designed explicitly to avoid the runtime register-allocation problem Keep in mind that ARM is RISC, it has no memory operands unlike x86-64. > changing this is...

> Support for signed division It just occured to me that signed integer division would introduce another edge case: `isize::MIN / -1` which overflows as the result is `isize::MAX +...

We should try to get the linker to concatenate similar sections (such as all read-only sections) and place them consecutively in virtual address space, so that we don't need to...

`sub imm` is kind of useless as it can be represented by `add imm` with a negative intermediate as well. However, swapping the operands so that the register is subtracted...

I finished the task "Restrict the callx jump targets to only allow known symbols": https://github.com/solana-labs/rbpf/pull/397 However, there are some new ideas what to add to SBFv2: - BTF for type...

> 3. With multiple entry points can those entrypoints return data to the client on an outer instruction? I understand the question being about the client, the one off chain...

> How will isolation work? Will the verifier enforce it? @leoluk Yes, that is the plan. On deployment the verifier would do type inference for the entire instruction stream and...

If you created the account with BPFLoader2 as owner (instead of gifting the account during program initialization), then it is finalized and thus the funds are burnt unfortunately. We should...