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Published 20 hours ago • verified publisher icon LibreDWG

Shorter compile times

Open rurban opened this issue 4 years ago • 1 comments
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Compile times are getting insane with 16GB RAM. Split out several shared libs of either modules, or object families (as Teigha does). With modules encode/decode split compile-time will still require >10min, only with the dwg.spec splitup it will become managable. so split out dynblocks and maybe acsh solids, surfaces

or maybe just upgrade to 32GB RAM (160EUR)

rurban avatar Jun 08 '21 06:06 rurban

The best solution so far is to use tinycc (CC=tcc), which is incredibly fast

rurban avatar Jul 12 '23 21:07 rurban