LIV2
Possible improvements
Hello,
I just finished reverse-engineering a silicon die shot of BUSTER. There are a few discrepancies between the extracted schematics and your verilog code. I'm not familiar with the Amiga so I can't really tell if those are from modifications needed for the CPLD to work, or consequences of guessing the logic by observing the signals ?
https://github.com/furrtek/SiliconRE/tree/master/Commodore/CSG5721
Hi @furrtek!
The logic was written based off observed behaviour and based on the pal equations from the German A2000 which was pre-Buster
It's great to see the reverse engineered schematics! I will study them and correct the Bluster logic to match soon. (I recently moved countries and my Amigas are still in transit)
After looking for a bit I've already noticed some small differences that will be easy for me to fix, and one expected deviation that is needed due to the faster timing of the CPLD.
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Chipram address should go up to $1FFFFF
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Reserved range should start at $B80000 not $A00000 https://github.com/LIV2/Bluster/blob/d5636e67cf82da5e60242252896920507d89563d/RTL/Bluster.v#L76-L77
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Collision circuit doesn't work as expected, XORing all inputs will not have the desired result (i.e an odd number of SLAVEs would not trigger a collision) https://github.com/LIV2/Bluster/blob/d5636e67cf82da5e60242252896920507d89563d/RTL/Bluster.v#L84
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DOE hack - An expected deviation from original - ASn buffered as DASn to deal with different timings of CPLD https://github.com/LIV2/Bluster/blob/d5636e67cf82da5e60242252896920507d89563d/RTL/Bluster.v#L90-L92