Adam Stylinski

``` [adam@odroid blah]$ cat source.c #include #include #include #include #include #include "adler32_p.h" #if defined(__clang__) || defined(__GNUC__) # define ALIGNED_(x) __attribute__ ((aligned(x))) #elif defined(_MSC_VER) # define ALIGNED_(x) __declspec(align(x)) #endif /* Minimum...

That's peculiar. I'm pretty sure our ci has an aarch32 target running neon (on Linux, at least). Does the crash go away if you remove the ALIGNED_(16) macro? There's no...

There's no obvious bug here that would trigger this. The loads themselves are of the natural type for a byte and the spills are generated by the compiler. The only...

I suspect clang is generating an alignment hint regardless at those stores. Now the address at the sigbus seemed properly aligned so that was weird but: https://github.com/android/ndk/issues/640 There's at least...

I _might_ be wrong here but I believe the swap is necessary if the element ordering happens to be critical. This has to do with the oddity that with VSX...

Yes it seems IBM's documentation is not being indexed very well by any of the search engines. I've routinely had this problem finding info on vmx/vsx. I'm not sure I...

> Note that the x86 concept of " execution ports" is somewhat unique and other architectures don't have the same bottleneck. > > You can see the Power scheduling characteristics...

> Power has decode groups, but most simple load, store, and vector instructions can occupy any slot and issue to any function unit. For performance, one assumes single threaded configuration...

To be clear, that is to say, from slowest to fastest, you have: vector8 < superscalar4 < vector4? I wouldn't expect the 8 sum version to be significantly worse like...

You say the SATA ports are all on the motherboard but are they all on the same SATA controller? A lot of boards get those high port counts by adding...