Boxcar rounding error

[grahamnaylormrc]

I am measuring phase using an adaptation of the phase noise example. This uses a complex multiplier of a DDS and the ADC in which is then roughly low pass filtered with the boxcar core and then a CIC core. We have been seeing systematic rounding errors that push highly filtered and averaged I and Q values to negative values due to the systematic rounding down by truncation (which always pushes towards negative). Although the random input from an LFSR to the multiplier reduces rounding errors in the multiplier, the boxcar core adds significant rounding errors (especially if width is only 16 bit). Rounding errors can be reduced by increasing the bit width and add a 0.5 offset before truncating . The code below would then be an alternative to the boxcar in the core provided (adds two +1 statements):

`timescale 1 ns / 1 ps

module boxcar_rounding_filter # ( parameter integer DATA_WIDTH = 16 ) ( input wire clk, input wire signed [DATA_WIDTH-1:0] din, output wire signed [DATA_WIDTH-1:0] dout );

reg signed [DATA_WIDTH+1-1:0] sum0; reg signed [DATA_WIDTH+1-1:0] sum1; reg signed [DATA_WIDTH+2-1:0] sum;

reg signed [DATA_WIDTH-1:0] din0; reg signed [DATA_WIDTH-1:0] din1; reg signed [DATA_WIDTH-1:0] din2; reg signed [DATA_WIDTH-1:0] din3;

always @(posedge clk) begin din0 <= din; din1 <= din0; din2 <= din1; din3 <= din2; sum0 <= din0 + din2 + 1; sum1 <= din1 + din3 + 1; sum <= sum0 + sum1; end

assign dout = sum[DATA_WIDTH+2-1:2];

endmodule