Pengcheng Xu
Pengcheng Xu
This issue documents the feature request by __@Catofes__ on Telegram. Work needed: - [ ] change config data structure to store multiple target paths in an array - [ ]...
As discussed in #1445, this is still a draft. - [x] basic signals for ACE4 and ACE4-Lite - [x] encodings for enums - [x] basic test for signals (checked locally,...
I'm looking at adding some support for ACE 4 on top of the `amba4.axi` classes we already have in `spinal.lib`, but I'm not super sure on what's the best way...
This draft PR is intended more as a discussion point; I don't think it can be merged as is. # Context, Motivation & Description I'm working on a slave design...
I understand that for Mem, a readWrite port can always host a read or a write port, so in principle the RAM with 1 readSync and 1 readWrite port should...
I'm trying out the plugin framework and encountered some deadlock issue: ```scala import spinal.core._ import spinal.core.fiber.Handle import spinal.lib._ import spinal.lib.misc.plugin._ class Plugin1 extends FiberPlugin { val logic = during setup...
In SpinalSim we now have the capability to interact with buses like AXI to read bits from the design. My design currently exposes some SpinalHDL `Bundle`, `Union` and `SpinalEnum` over...
I have a input stream to the AXI DMA with "holes" (i.e. `tkeep[...] = 0`). Per AXIS specification, these bytes should be discarded. However, the DMA module does not behave...
Following #1337, `PackedBundle` seems like a perfect candidate to define external instruction words with holes inside the definition. However, I'm not sure how I can fit them inside a `Union`....
--- **From the maintainer Li Haoyi**: I'm putting a 500USD bounty on this issue, payable by bank transfer on a merged PR implementing this. The task is to appropriately detect...