JoyBed

I can compile with these changes and get MMU support on Linux?

> I would love to see such functions so we can utilize PS memory as main_ram and debug soft-core from PS side. Potentially I can work on litex_server on PS...

Well... When I limit it in the dts to 512mb then the linux can boot but the biggest problem I always had is NaxRiscv. The main_ram works on ANY softcore...

I used this: ./xilinx_zybo_z7_20.py --variant=original --cpu-type=naxriscv --xlen=64 --scala-args='rvc=true,rvf=true,rvd=true,alu-count=2,decode-count=2,mmu=true' --with-fpu --with-rvc --with-ps7 --bus-standard=axi-lite --with-spi-sdcard --sys-clk-freq=125e6 --with-xadc --csr-json zybo.json --uart-baudrate=2000000 --build --update-repo=wipe+recommended --vivado-synth-directive=PerformanceOptimized --vivado-route-directive=AggressiveExplore --with-hdmi-video-framebuffer --l2-bytes=262144 --l2-ways=16 --with-jtag-tap When I generate a...

> > when I generate it with DRAM connected to pbus > > Hmm should realy not do that, the Nax SoC is realy intended to use cacheable memory through...

> Maybe the reason why this isn't working, is that if let's say, we specify that the memory is on the AXI bus at 0x40000000, then naxriscv can access it,...

> > So a access to 0x45000000 thru mbus emits address 0x05000000 ? > > > > Yes, i need to double check but that is quite possible. I tried...

> I'm looking at it. Trying to get the offset to be preserved. > > > > Also, did you tried vexriscv_smp cpu ? Yes, and it was working and...

Very strange behaviour, thru mbus it locks up at mem_test evne when i specified no L2 cache. I also tried it again with dram to pbus without L2 to see...

Also if the DRAM is connected thru pbus and I just bypass the non functional addresses then it can even boot:  Even linux booted when I specified in device...