Triton

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Support for ARM32 ldm<amode>

5

Would it be possible to add support for different `` (`DA`: Decrement After, `DB`: Decrement Before, `IA`: Increment After and `IB`: Increment Before) in instructions such as `ldm` (or `stm`)?...

pdamian

Taint propagation on conditional jumps

1

Consider the x86 instruction `JG` for example, where the jump is taken if `ZF = 0` and `SF = OF`. If `ZF` has an untainted, concrete value of `1`, then...

namreeb

Setting symbolic memory with concrete value using SYMBOLIC_STORE and SYMBOLIC_LOAD doesn't concretize the memory

3

Evening, I was recently making use of `triton::modes::SYMBOLIC_STORE`, `triton::modes::SYMBOLIC_LOAD` with `triton::modes::MEMORY_ARRAY` as it seemed to be perfect when acting in arbitrary context. Except that when attempting to concretize a previously...

ek0

Clang format

7

I've tried to minimize the diff but also didn't want to exactly match it to get somewhere in the middle of readability and consistency. I also enabled the option to...

ZehMatt

This allows you to build a single python wheel for all versions of python. Reference: https://docs.python.org/3/c-api/stable.html Example workflow: https://github.com/icicle-emu/icicle-python/blob/main/.github/workflows/CI.yml

mrexodia

Add .clang-format to the project

3

It would be really nice to have this, the format is quite mixed and would help contributors think less about the code style and focus more on the technical aspect....

ZehMatt

Question: enhancing code coverage with external tracers

6

In order to increase the code coverage, I want to solve the unsolved branches. Sample target does only string comparison (strcmp) . My tarcer was IntelPin/Dynamorio, I sent execution information...

alexsetsove

windows 16bit and 8 bit registers not simplified

2

code ```python from triton import * ctx = TritonContext(ARCH.X86_64) block = BasicBlock([ Instruction(b"\x66\xBE\x00\x00"), # mov si, 0 Instruction(b"\x66\xBE\x01\x00"), # mov si, 1 ]) print('[Original basic block] ----------------------------------------------- ') ctx.disassembly(block, 0x140004149)...

NaC-L

As a follow-up to my previous issue, I would like to know if Triton has a functionality that can link the following instructions with backward slicing: 1: sub $0x1a8,%rsp 2:...

antonislouca

Reduce usage of concrete evaluation in x86 semantics

19

Hi @JonathanSalwan, In [x86semantics.cpp](https://github.com/JonathanSalwan/Triton/blob/master/src/libtriton/arch/x86/x86Semantics.cpp), there are 46 instruction handlers where the emitted ASTs are dependent upon a concrete value retrieved through `.evaluate()`: - [ ] x86Semantics::cmpsb_s - [ ] x86Semantics::cmpsd_s...

Colton1skees