Jan Matyas

Use ULL (unsigned long long) suffixes in generated encoding.h file

2

Improvement suggestion (merely a note to self): The integer literals in the generated `encoding.out.h` C header file should contain `ULL` suffixes (`unsigned long long`) when the actual value exceeds 64...

Note to self: Function for System Bus read operation `read_memory_bus_v1()` uses low-level JTAG operations (functions `jtag_*()`) to carry out the DMI operations. Rewrite this function to use the proper DMI...

Note to self: - Check value of dtmcs.abits, read from the target. It should be in range `7..32`. - Data type for DMI address inside OpenOCD should be changed to...

Note to self: Discovered by code review that the following variables should be unique per each target (not globals shared by all RISC-V targets): - `select_dtmcontrol` - `select_dbus` - `select_idcode`...

The function `deassert_reset()` in riscv-013.c should be updated to set the `dcsr.ebreak*` bits as configured by `riscv set_ebreakm`, `set_ebreaks` and `set_ebreaku` commands. This is especially important when the TCL `reset...

Multiple issues related to resuming and breakpoints

2

While debugging a local issue and analyzing the code of riscv-openocd, I came across multiple issues that relate to resuming/stepping and how breakpoints/triggers are handled. Since I don't have the...

Code improvement: Refactor functions that select implentation based on debug spec version

1

Note to self: In functions like [resume_go()](https://github.com/riscv/riscv-openocd/blob/1730287e1fedc6b369f2c4244da7509c53c9f0fb/src/target/riscv/riscv.c#L1470), consider the use of the following: - explicit `if` for the debug module spec version - direct function calls to the 0.11 vs....

A note to self: `riscv_*` functions should not be called too early (before the target is fully examined), as noted in this comment: https://github.com/riscv/riscv-openocd/blob/1730287e1fedc6b369f2c4244da7509c53c9f0fb/src/target/riscv/riscv-013.c#L1704 Add assertions to the `riscv_*` functions,...

A small addition to README.md: Added location of SweRV JTAG signals on JD connector of Nexys A7 board (table + picture). Ths is to make the instructions easier to follow...

(Note to self:) Currently, OpenOCD keeps track whether abstract register access is supported for CSRs and FPRs as whole register "class". That is, OpenOCD keeps just one bool flag for...