Jan Matyas

Closing this thread since the feature has been implemented in: https://github.com/riscv/riscv-openocd/pull/875

`test_sba_config_reg` has already been removed in https://github.com/riscv/riscv-openocd/pull/780 Closing this issue.

Hi @monniaux, yes, you are right. The demo in this repository is designed so that JTAG interface of the SweRV CPU is exposed on pins of the JD connector on...

Hi, your JTAG wiring appears all right - I do not see any issue with the physical connection. I'm wondering what SweRV version you use. Do you use 1.4 or...

Feel free to use 1.5. In that case, however, you need to adjust the RTL prior to the synthesis. See my previous comment.

The most important message from your OpenOCD log is: `Error: 229 68 core.c:1132 jtag_examine_chain_check(): JTAG scan chain interrogation failed: all ones.` This means that JTAG TDO signal is for some...

Hi @zhuzhizhan, to my knowledge, this Cores-SweRV_fpga repo hasn't been well maintained recently. Please look at https://github.com/chipsalliance/Cores-SweRVolf for a well-maintained alternative. Jan