Jan Matyas

Hi @allexoll, thank you for reporting this. Correct, on a RV32 core, as in your case, at least two data registers are required to perform the abstract memory access. (So...

> I think the first option would make more sense, I would prefer implementing both the items i. and ii. I'll have time to submit the change within approx. a...

Hi Sujay, Thank you for filing this ticket. I can confirm this is a valid issue. All bits in "abstractauto" DM registers are optional per the RISC-V Debug specification, and...

If I understand correctly, the change from this merge request was merged (in a modified form) via #768. Can this one be closed, then?

My proposal would be to specify the external debugger is permitted to perform `dmactive

I maintain the opinion that - if a DM that is reset (via `dmcontrol.dmactive Since the ED does not know whether the target is 0.13 or 1.0 compliant at this...

> ... whoever handles it needs to do it in such a way that the constants can still be used in assembly code, where the ULL suffix will cause a...

Closing this outdated merge request. The main problem appears to be that `riscv_openocd_step()` reports resume + halt to GDB every time, but "internal" steps (e.g. when resuming from a trigger)...

@zqb-all: Do I understand correctly that you refer to case when there are multiple DMs on a single DMI bus? The first one located at DMI address 0, the other...

@zqb-all You're correct, this is unfortunately still not supported as of now. If there is need to implement that feature, this is roughly what it would take: - The DMI...