Jan Matyas

> I'm new in FPGAs and wondering how does your bscan_tap module work ? Hi @agrobman, The `bscan_tap` module in SweRVolf is a wrapper over Xilinx BSCANE2 primitives, provided only...

> FTDI chip has two serial channels can be configured as JTAG IFs, > > Can the 2nd one be connected/used as original swerv JTAG interface to test original JTAG...

> a) there is no TRST line in their adapter/pin connector. Correct, in Digilent JTAG HS2 there is no TRST output. From user perspective, this is not important. TRST is...

> or solder these two pins to some FPGA IO/connector (QFP package pins are exposed to soldering ...) > Oh, they actually confirmed that we CAN connect/solder these pins with...

> I meant to use FPGA TDI/TDO/TCK/TMS pins as SweRV JTAG pins. Does Vivado allow to reuse these pins for emulated design? My understanding is that TDI, TDO, TCK &...

> Jan, BTW, did you ever use/check original SwerV DMI module in FPGA emulation with any debugger? Yes, I have worked with plain-vanilla SweRV w/ original DMI & JTAG interface...

Hi @MatthewMFLai, so this is not SweRVolf-related question, all right. In general, if you work with a 3rd party design on Nexys A7 board, it is best to ask the...

> What testing have you done for this? I've tested this internally against the LLDB debugger (which speaks the GDB Remote protocol, same as GDB). Without the patch, the debugger...

> Assuming e.g. all the spike32-2 tests from riscv-tests/debug pass then I'm fine merging this. I've run the riscv-tests on this change here: https://github.com/JanMatCodasip/riscv-openocd/pull/3 It turns out the impact of...

Hi kingstone1927, This appears not to be an issue of OpenOCD. Current version of OpenOCD is known to work fine with SweRV. It is more likely a problem with SweRV...