Indan Zupancic

The IPC1001-3 tests are very slow on real RISC-V hardware too, wouldn't surprise me if emulated SMP RISC-V in QEMU is even worse. It's on my todo list to look...

I'm in favour. Considering that `DebugException` is always 4, I think it may have been a mistake to make the fault numbers different for MCS. There is no reason why...

> The better fix would be to upgrade `cmake-format` to something more recent, then we could drop a lot of the version requirements again. How do you want to proceed?...

> Putting this on draft for now to keep it here until cmake-format is bumped. This PR should be closed once that is done and is working. Has that been...

> So from a purely theoretical perspective, there shouldn't be an issue with patching the value of the const domain schedule? What then was the issue that caused this to...

Indeed it does. Practically that means that `seL4_TCB_SetSchedParams` can only be called once when creating the TCB for the first time and that it's useless to update parameters later on....

Normally you would use the `SEL4_FORCE_LONG_ENUM` trick when you want to define the enum size when used within a structure. But I don't think seL4 does that, for verification it's...

Considering you want to turn on a real CPU core, I don't see why you would need to use a HVC call instead of a SMC call for that. HCV...

> I attempted to get 32-bit ARM working but ran into two problems: > > 1. At least for the PSCI version that QEMU expects, the SMC/HVC function IDs are...

> > That doesn't make any sense, is this another Qemu quirk? > > I was looking at [this](https://documentation-service.arm.com/static/6703a8b8d7e4b739d817e10d) PSCI specification (DEN0022F.b_Power_State_Coordination_Interface). Section 5.1.4 says the function ID for SMC32...