Indan Zupancic
Indan Zupancic
> My bad, I thought people were already aware that it affects GICv2 as well. No worries, it's still good to document it or double check whether it is known...
I agree that not passing `thread_control_sched_update_sc` makes more sense when `tcb->tcbSchedContext == sc` (which implies `sc->scTcb == tcb`).
> But my initial thoughts on this were that the old error behaviour was much more clear, The old behaviour was to always fail the call if the thread already...
It shouldn't: XSAVE is an unprivileged instruction, you can do it even in user space. Just make sure `CR4.OSXSAVE[bit 18] = 1`, see [here](https://www.felixcloutier.com/x86/xsave). Edit: To elaborate, it shouldn't matter...
What platform are you using, what errors do you get and did you check if your seL4 compile/config options match the ones you use for user space and the QEMU...
> 1. I am under the impression that seL4 should not have nested exceptions (in normal operation). True, it keeps IRQs disabled while in kernel mode. > 4. We should...
I'm going to be annoying and say that `intStateIRQNode` doesn't need to be power-of-two. Yes, it's kind of a CNode, and yes, CNodes are assumed to be power-of-two, but no...
I don't know how it is on RISC-V and x86, but for Arm the main downside would be that the kernel currently uses one large 2 MB page for everything....
Could try `qnx` instead of `linux`, or not use legacy bootm any more.
> Sorry, not sure what relevance creating new files has with layout in memory? Like obviously it will affect it but so will the phase of the moon. If you...