Indan Zupancic
Indan Zupancic
> The GICv3 hw does support sending to up to 16 cores at a time using a 16bit target mask. This is only any good if we do something similar...
This relates to https://sel4.atlassian.net/browse/RFC-15. I converted this to draft as it doesn't seem ready yet.
I think treating Morello as a CPU type is wrong and will lead to problems in the future when there are multiple hardware Morello implementations. So I think there should...
> > This relates to https://sel4.atlassian.net/browse/RFC-15. I converted this to draft as it doesn't seem ready yet. > > RFC-15 is mainly about CHERI support, this is just another AArch64...
(And feel free to remove it from draft status.)
> In the Arm world, "Morello" is being interchangeably (and confusingly) used to represent an architecture[extension], an SoC, a CPU, and a board. That is highly confusing and I want...
Any particular reason why using GICv2 instead of GICv3?
> Two reasons, the first is that I don't think GICv3 is completely properly emulated in QEMU; I don't see any open bugs related to GICv3 in QEMU. Main thing...
> > So it seems worth looking into, it may be overly strict. If it works without the `halt()` we can leave it in as a warning, but it doesn't...
> I don't think it's FPU related either, this test requires scheduling, so I suspect we're not getting timer interrupts at all. It hangs with GCC and Clang. A quick...