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Published 20 hours ago • verified publisher icon IHP-GmbH

KLayout: PMOS and NMOS have different GatPoly Layers

Open vkrahul77 opened this issue 11 months ago • 2 comments

In the "IHP Pycells", For Gate The PMOS has "GatPloy.lbl" while NMOS has "Gatpoly.drw" as shown: GatePloy_PMOS_NMOS

Also, I've noticed a discrepancy in dimension input between NMOS and PMOS transistors within the tool. Specifically, while "1u" notation is accepted for PMOS, it's not permitted for NMOS. Instead, we're required to use scientific notation such as "1e-6".

vkrahul77 avatar Mar 07 '24 06:03 vkrahul77

it seems to be an issue in both nmos and pmos cells - there should be no any '.lbl' or '.bnd' GatPoly layers, only '.drw' and '.pin'.. Thank you for finding!

ihpopenpdk avatar Mar 07 '24 20:03 ihpopenpdk

Along with the posted bug, I noticed that there are a few DRC errors in NMOS-Cell. Here is a list: Min and Max size of contact should be 0.16 --> Cell has 0.14 Min Contact space should be 0.18 --> Cell has 0.16 Min Metal1 space or notch should be 0.18 --> Cell has 0.13 image

vkrahul77 avatar Mar 12 '24 22:03 vkrahul77

@vkrahul77 , I believe all these issues are fixed in the latest OpenPDK dev branch: image

sergeiandreyev avatar May 18 '24 12:05 sergeiandreyev

Hi @vkrahul77, can we close the ticket? Do you have any additional comments?

sergeiandreyev avatar Jul 10 '24 09:07 sergeiandreyev

Sure! Please go ahead and close the ticket. Sincerely, Vikas

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vkrahul77 avatar Jul 10 '24 09:07 vkrahul77