Misato RISC-V RV32I CPU

Misato is a RISC-V CPU that supports the RV32I instruction set. It has not won any awards (yet) but it has FuseSoC support! It is formally verified in that each instruction performs what and when it is supposed to perform. Currently it requires separate, single-cycle instruction and data memories, but in the interconnect branch I'm working on a Wishbone Classic interface (which does not pass formal verification yet). The core is written in Amaranth HDL.

Status

All RV32I instructions have been implemented except for FENCE, ECALL, and EBREAK.

It has been implemented with a 65 nm PDK and the Skywater 130 nm PDK using OpenLANE by the award-winning Olof Kindgren.