GuzTech

I have the same issue as the OP. To reproduce, simply run litex_sim.py using upstream LiteX. In my case, the contents of the VCD file just stops abruptly, indicating the...

Fair enough, I'll see if I can whip up something for the ECP5 and share it here.

I have an initial implementation in #426.

Here are some of my thoughts on how a PLL could be used: #### PLL Creation As I see it, there are three ways of creating a PLL. 1. Create...

> It seems to me that it's worthwhile to start with the frequency problem. Do you think you can start collecting the info about PLLs and expressing it in the...

Ok, I'll look up the formulas from the datasheets for each PLL. The data representation should express the equations symbolically using a symbolic expression library I assume.

Yes, I agree. To a user, it shouldn't matter *how* the parameters are being resolved, as long as the specification of input/output frequencies/phases is designed correctly.

I would want it to be as general as much as it makes sense. I think most of the issues you mentioned can be solved if we can specify the...

Yeah, you're right. I got confused :) Output clocks are routed through dedicated clock networks, so it doesn't really matter. I would matter if they were to be routed through...

## iCE40 Family Both the LP and HX parts have the same constraints when it comes to PLL parameters. The parameters are: 1. fIN - Input clock frequency. Related signals:...