descrypt-ztex-bruteforcer
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Gifts
supported hardware and future work?
Which ZTEX FPGAs are supported by this code?
Also, how many man-hours might be needed to make the improvements that you're hoping for?
Which ZTEX FPGAs are supported by this code?
ZTEX 1.15y boards are the primary target, but due to verilog this code can be used with any Xilinx FPGA with resources at least as those in XC6SLX100 chip.
Also, how many man-hours might be needed to make the improvements that you're hoping for?
Hard to say, for now I am doing some research with the same DES-core regarding on-chip candidate passwords generation and hash comparison (not as easy to implement, as it seemed). Unfortunately, I can't dedicate as much time as I want for this project.
I'm open for any help =)
I'm not a programmer, but I am interested in seeing more work in this space. I've also been talking with the John the Ripper folks. They might be able to collaborate with you. I would love to see this support directly in JtR.
The 960Mh/s number is the aggregate for the entire 1.15y board (four Spartan 6 chips), I assume?
I would love to see this support directly in JtR.
So do I, it would solve many of the problems.
The 960Mh/s number is the aggregate for the entire 1.15y board (four Spartan 6 chips), I assume?
Yes, it is aggregate speed. For now this design works at 240 MHz with 1 hash per tick. There are plenty of space in chip to do 2 hashes per tick, and in would take some effort to do 4 hashes per tick in exchange of plain chip speed.
Are there any plans to release the resulting bitstream directly, so that people without the Xilinx ISE can use this work? I'm not knowledgeable in this space, so I'm not sure what is feasible.
Adding a note for future searchers that John the Ripper jumbo now has support for ZTEX 1.15y boards. It's not enabled by default -- configure with --enable-ztex. Related tools at https://github.com/Apingis.