Instruction offset

[adam-yang]

Hi, I'm trying to construct the control flow graph from asm using the IsaDecoder. The branch instructions give the branch offset, but there's no information about instruction's offsets. Is there a way to achieve what I'm trying to do?

Thanks.

[AmitBM]

Hi @adam-yang,

Did you use DecodeShaderDisassemblyText() / DecodeShaderDisassemblyFile() with resolve_direct_branch_targets set to true? You will need to decode the whole shader in order to enable branch resolution.

[adam-yang]

Here's all the input I've tried (all except the binary file attached):

1. Dissassembly (attached)
2. Content from .text section from the binary ELF

For both was able to see inst.instruction_semantic_info.branch_info.branch_offset, but no branch target information was available. It looks like the disassembly was not being used at all, and IsaDecoder was using the information in the comments? Is this the intended final behaviour?

Would it be feasible for IsaDecoder to give the offset for each instruction, this way I can use branch_info.branch_offset to figure out the control flow, as well as use the offset to find source mapping from debug info?

This assembly is from RDNA 3.5. s_code_end was also being shown as a branch.

simple.asm.txt simple_from_elf.asm.txt

[AmitBM]

Hi @adam-yang,

Are you getting BranchInfo::branch_target_index populated? That field should give you the index of the target instruction within the Decode* function's output vector (std::vector<InstructionInfoBundle>).

-=-=-=-

Regardless - How did you generate the disassembly? It is "non-standard" (compared with the shader disassembly format that AMD tools normally produce):

1. simple_asm.txt does not contain any labels (for branch targets).
2. simple_from_elf.asm.txt does not contain the standard comment (// <offset>: <binary representation>).

Also please note that the label name format is unusual as well (".L*") - this may cause issues with some other AMD tools but shouldn't impact IsaDecoder.

The IsaDecoder API currently relies on the disassembly format being "standard". That is why you did not get all branch metadata fields populated. Item '1' above can be addressed (the presence of labels should not impact branch resolution) - that should be fixed. Item '2' above is required by the IsaDecoder API in its current implementation. It would be good if you could work with the "standard" AMD disassembly format if you are planning to leverage the isa_spec_manager toolset.

[adam-yang]

Hi Amit,

The branch target is not populated. The following is information about the two branch instructions from using binary input, for the same assembly attached earlier.

S_CBRANCH_EXECNZ

  branch_offset:       -52
  branch_target_pc:    ""
  branch_target_label: ""
  branch_target_index: 18446744073709551615
S_CBRANCH_EXECZ
  branch_offset:       14
  branch_target_pc:    ""
  branch_target_label: ""
  branch_target_index: 18446744073709551615

I attached the repro in this comment. simple.o is the full ELF file. simple.o.bin is just the code section.

simple.zip

================================================================= simple_asm.txt is from a driver pipeline dump. simple_from_elf.asm.txt is elf printed out via LLVM tools.

What is considered "standard" disassembly format? What tool produces standard disassembly?

[AmitBM]

Hi @adam-yang,

Thanks for sharing the input files.

The attached file contains your shader's disassembly in a "standard" format - disassembly_cs_adam-yang.txt

You can generate that disassembly using RGA's Binary Analysis mode -

1. Download the latest RGA release from the RGA GitHub Releases page.
2. Run RadeonGPUAnalyzer.exe and select Binary Analysis mode.
3. Rename "sample.o" -> "sample.bin" & drag and drop it in the RGA GUI application.
4. After the binary is successfully analyzed, you will see the shader disassembly in RGA. To get the raw text file, right-click anywhere on the disassembly and select "Show disassembly file in explorer".

If you call IsaDecoder::DecodeShaderDisassemblyFile() with resolve_direct_branch_targets == true, you should see the branch info populated properly -

Note that RGA is using amdgpu-dis in this case to disassemble the Code Object (ELF) file, but in other use cases it may use llvm-objdump. Both tools (and other AMD official tools) should generate disassembly in a "standard" format. If you are using an official AMD tool to generate shader disassembly and get a different shader disassembly format, please let me know.