German Forth Conference 5-8 April 2018

[cstrotm]

Hi,

the German Forth Conference will take place in Linuxhotel in Essen (https://linuxhotel.de) from 5.-8. April 2018.

Day 0 (Thursday) will have tutorials and possibly a Forth Standard meeting, the regular conference starts Friday noon and runs until Sunday noon.

A couple of interesting talks will be given:

• Gerald Wodni: T800: A modern Forth IDE
• Manfred Mahlow: Forth WORDLISTs in Flash
• Mandfred Mahlow: STM8 eForth
• Bernd Paysan: net2o progress report
• Anton Ertl: Generalization of "locals"
• Klaus Zobawa: Porting Mecrisp-Stelaris to Cypress PSoC-5LP
• Joerg Voelker: T4 - Reloaded
• Joerg Voelker: compact and fast - and experimental Forth
• Ullrich Hoffman: preForth - a minimal bootstrap Forth-Kernel
• Jens Storjohann: Generic programming
• Carsten Strotmann: sixel graphics from forth

usually the conference language is german, but if non-german Forth enthusiasts attending, most speaker will be able to switch to english.

Registration is still open at http://tagung.forth-ev.de/

Hope to see you there

Carsten

[larsbrinkhoff]

STM8! Sixels!

CC @aap.

[hth313]

Sounds very interesting, but I am totally unable to attend (and I do not understand german that well either).

I notice that the titles are in english. Is there any chance of some published papers or video recordings of this event?

[forthy42]

I will record all talks and put the videos online here, as usual (since 2013):

https://wiki.forth-ev.de/doku.php/events:start

[TG9541]

Thanks for bringing the talks on-line - too bad that I can't attend the meeting.

[lowfatcomputing]

So many intriguing talks for Forth-Tagung 2018!

"Porting Mecrisp-Stelaris to Cypress PSoC-5LP"

I did a port of mecrisp-stellaris to PSoC 5LP roughly a year or two ago. I was writing a USB driver for it in arm asm but then just switched to a temporary bitbanged uart.

https://hub.darcs.net/pointfree/mecrisp-stellaris-cy8c5888-bb

It's rudimentary but it works. It has no uart flow control or compiletoflash support, but I could add it. Klaus Zobawa's port may have these things already and other features I haven't yet touched. We should probably be collaborating :-)

ping @Mecrisp

Regarding PSoC 5LP forth, I've been spending most of my time on the PSoC 5LP's logic fabric (something like a CPLD). Essentially adding "compiletologic": this means the same set of core words are implemented in ARM assembly and Forth-based HDL.

I did move away from mecrisp-stellaris and stacks towards my own fifo-based forth: http://www.0xff.in/bin/SVFIG-Jan27-2018-The-Case-for-FIFOs-in-Place-of-Stacks.pdf

I think I'll stick with fifo-based forth because:

• parameter juggling is pretty much absent.
• Stacks are good for keeping most frequently used items on top and temporarily forgetting about items deeper down the stack. I have never seen a forth parameter stack benefit from this. I've never seen a good forth programmer leave junk in the parameter stack and forget about it.
• it's a better fit for the inherently dataflow-based configurable logic fabric.
• fifos are amenable to lazy evaluation which I intend to use for dynamic on-chip logic synthesis. Keep in mind the entire logic fabric configuration is memory mapped. Furthermore the signals flowing through the routes are accessible by firmware through the status and control blocks in each (internal) UDB block and of course the DSI to portpins and other peripherals.

I can once again easily use forth sixels in my preferred terminal emulator (termite). Yay!

https://www.reddit.com/r/Forth/comments/59drtc/forthsixel_sixel_raster_graphics_in_your_terminal/

I'm also redoing the forthy sixel graphics in fifo-based forth and applying lazy evaluation for (faster) minimal updates of an image.

I think sixel graphics is a great way to add graphics to an embedded microcontroller forth and it looks like support for it is increasing in distros and terminal emulators. I very much look forward to your talk @cstrotm !

EDIT: I realized I can turn stack words into fifo words very easily in mecrisp-stellaris with: : >q depth 1- -roll ; https://hub.darcs.net/pointfree/mecrisp-fifos

[cwpjr]

I think I will look into fifo forth to see how well it fits functional programming.

On Mon, Mar 19, 2018 at 12:58 PM, Andreas Wagner [email protected] wrote:

So many intriguing talks for Forth-Tagung 2018!

"Porting Mecrisp-Stelaris to Cypress PSoC-5LP"

I did a port of mecrisp-stellaris to PSoC 5LP roughly a year or two ago. I was writing a USB driver for it in arm asm but then just switched to a temporary bitbanged uart.

https://hub.darcs.net/pointfree/mecrisp-stellaris-cy8c5888-bb

It's rudimentary but it works. It has no uart flow control or compiletoflash support, but I could add it. Klaus Zobawa's port may have these things already and other features I haven't yet touched. We should probably be collaborating :-)

ping @Mecrisp https://github.com/mecrisp

Regarding PSoC 5LP forth, I've been spending most of my time on the PSoC 5LP's logic fabric (something like a CPLD). Essentially adding "compiletologic": this means the same set of core words are implemented in ARM assembly and Forth-based HDL.

I did move away from mecrisp-stellaris and stacks towards my own fifo-based forth: http://www.0xff.in/bin/SVFIG- Jan27-2018-The-Case-for-FIFOs-in-Place-of-Stacks.pdf

I think I'll stick with fifo-based forth because:

• parameter juggling is pretty much absent.
• Stacks are good for keeping most frequently used items on top and temporarily forgetting about items deeper down the stack. I have never seen a forth parameter stack benefit from this. I've never seen a good forth programmer leave junk in the parameter stack and forget about it.
• it's a better fit for the inherently dataflow-based configurable logic fabric.
• fifos are amenable to lazy evaluation which I intend to use for dynamic on-chip logic synthesis. Keep in mind the entire logic fabric configuration is memory mapped. Furthermore the signals flowing through the routes are accessible by firmware through the status and control blocks in each (internal) UDB block and of course the DSI to portpins and other peripherals.

I can once again easily use forth sixels in my preferred terminal emulator https://github.com/thestinger/termite/issues/539#issuecomment-362679869 (termite). Yay!

https://www.reddit.com/r/Forth/comments/59drtc/forthsixel_sixel_raster_ graphics_in_your_terminal/

I'm also redoing the forthy sixel graphics in fifo-based forth and applying lazy evaluation for (faster) minimal updates of an image.

I think sixel graphics is a great way to add graphics to an embedded microcontroller forth and it looks like support for it is increasing in distros and terminal emulators. I very much look forward to your talk @cstrotm https://github.com/cstrotm !

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[Mecrisp]

I did a port of mecrisp-stellaris to PSoC 5LP roughly a year or two ago. I was writing a USB driver for it in arm asm but then just switched to a temporary bitbanged uart.

https://hub.darcs.net/pointfree/mecrisp-stellaris-cy8c5888-bb

It's rudimentary but it works. It has no uart flow control or compiletoflash support, but I could add it. Klaus Zobawa's port may have these things already and other features I haven't yet touched. We should probably be collaborating :-)

ping @Mecrisp https://github.com/mecrisp

Here I am, my congratulations !

I would be glad to add your conquest to the mainstream release. I already have a similar level of support for PSOC4, bit-banged UART, no compiletoflash. Thank you for the hints that made this possible.

I am currently in touch with Klaus Zobawa, his port can do much more, but it is tied to the Cypress Creator and makes use of (a lot of) generated C code.

Therefore, both ports should be available, yours as completely free and understood, a great starting point for those wishing to go bare metal, and the one of Klaus which takes advantage of everything Cypress has libraries for, which, alas, cannot be built with entirely open source tools.

By the way, I have a partial M3 emulator up and running now, so you can write USB driver in Forth and turn this into a precompiled binary before flashing into the target chip.

Regarding PSoC 5LP forth, I've been spending most of my time on the PSoC 5LP's logic fabric (something like a CPLD). Essentially adding "compiletologic": this means the same set of core words are implemented in ARM assembly and Forth-based HDL.

I need to wrap my mind around that. Logic synthesis from Forth ? Marvellous !