FPGAwars
bug: Icestudio generates verilog code that doesn't pass lint.
Steps To Reproduce
The details and reproduction steps are in this apio issue https://github.com/FPGAwars/apio/issues/537. Icestudio generated verilog code doesn't pass 'apio lint'.
Example:
+ apio lint
Setting the environment.
Processing board ice40-hx8k
----------------------------------------------------------------------------------------------------------------------------
Creating verilator config file.
Scanning for issues.
verilator_bin --lint-only --quiet --bbox-unsup --timing -Wno-TIMESCALEMOD -Wno-MULTITOP --top-module main -DNO_ICE40_DEFAULT_ASSIGNMENTS -I"/Users/user/.apio/packages/oss-cad-suite/share/yosys/ice40" _build/hardware.vlt "/Users/user/.apio/packages/oss-cad-suite/share/yosys/ice40/cells_sim.v" main.v
%Warning-PINMISSING: main.v:486:10: Cell has missing pin: 've37344'
486 | v97d607 v2299cf (
| ^~~~~~~
main.v:927:9: ... Location of port declaration
927 | output ve37344
| ^~~~~~~
... For warning description see https://verilator.org/warn/PINMISSING?v=5.031
... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Error: main.v:1295:6: Duplicate declaration of signal: 'q'
: ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2023 23.2.2.2)
1295 | reg q = INI;
| ^
main.v:1292:9: ... Location of original declaration
1292 | output q
| ^
scons: *** [_build/hardware] Error 1
=============================================== [ ERROR ] Took 0.52 seconds ===============================================
Expected behavior
Icestudio generated apio project pass 'apio lint' with no error. (Using apio dev).
Actual behavior
Apio lint fails on Icestudio generated verilog code.
Screenshots or video
No response
Desktop (please complete the following information)
No response
Web console trace
Additional context
No response
Some additional info: (using Windows)
When I clone the dev branch and use npm start to launch the dev environment version of icestudio, when I build a relatively simple project and upload it to the board (using https://github.com/FPGAwars/iceBoards/blob/main/examples/Icesugar-1.5/02-jumping-LED.ice), the state machine doesn't run and the board just "hangs" with the RGB led lighted blue.
If I build the same project using v0.12 stable, installed using the windows installer downloaded from the main download link, then this very same project works just fine after building and uploading. Modifying the project to output more wires to a PMOD also works just fine, etc.
But this may be another (possibly related) problem so I'll file another issue and collect the verilog output.
Hi @rjstone !, dev branch is now in very heavy development state and could be breaking changes. At the middle of July the development version should be in very "stable" and non breakable state, but the next weeks a lot of changes are comming.
@cavearr Ok I will hold off on trying to do anything with the dev branch and just put a "watch" on the icestudio repo waiting for a better time to give some stuff a try.