Peter Lebbing

Perhaps active development has shifted to https://github.com/acme-dns/acme-dns-client? It's what I use now anyway.

I gave it a try. Too late for camp though :-).

I was just playing a bit; it resulted in four observations. I did this: ```diff --- a/clash-lib/prims/vhdl/Clash_Sized_Internal_BitVector.primitives.yaml +++ b/clash-lib/prims/vhdl/Clash_Sized_Internal_BitVector.primitives.yaml @@ -533,6 +533,9 @@ type: 'shiftR# :: KnownNat n => BitVector...

Note that I was thinking we should have functionality to emit constraints on top-level ports like we can with [SynthesisAttributes](https://hackage.haskell.org/package/clash-prelude-1.6.3/docs/Clash-Annotations-SynthesisAttributes.html) but more generic. In Quartus, you can use those attributes...

Right, I think I understand what you are going for. I was noting it would be even better to have a more general mechanism; and I believe what we'd really...

> I think you'd still want the names, or at the very least require some way to link a register/wire in code to a constraint. How would you imagine how...

This issue got rather silent so I picked it up and discussed it in real life with @leonschoorl . He pointed out that the proposed naming of the registers with...

Ah, interesting to see development in this part! 1. I don't think common functionality should be in `clash-testsuite`, that is a package with a very narrow, specific purpose. And if...

Ah no, I had actually thought we had decided this was to be closed and superseded by #2321, so there was a bit of miscommunication. There is no need for...

For other blockRAMs, we implement Read First and then provide [`readNew`](https://hackage.haskell.org/package/clash-prelude-1.5.0/candidate/docs/Clash-Explicit-BlockRam.html#v:readNew) to adapt that into Write First. A similar adapter could be written for No Change. Has this option been...