Jerry
Jerry
https://github.com/chipsalliance/rocket-chip/blob/46c88b71056581a6bf2a0c4febd5ec3d768c6c59/src/main/scala/diplomacy/Nodes.scala#L995 The comment indicates allSink means `The total number of :*= operators where we're on the left.` I think it is very confusing using 'we' here. From my understanding, allSink...
this is the comment of `CustomNode,` ` A [[NodeImp]] that may be extended with custom behavior.` which is an obvious error, It should be `MixedNode` or `MixedCustomNode` https://github.com/chipsalliance/rocket-chip/blob/46c88b71056581a6bf2a0c4febd5ec3d768c6c59/src/main/scala/diplomacy/Nodes.scala#L1316
### Background Work - [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard) - [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues) - [X] Yes, I searched the [documentation](https://chipyard.readthedocs.io/) ### Chipyard Version and Hash...
### Background Work - [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard) - [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues) - [X] Yes, I searched the [documentation](https://chipyard.readthedocs.io/) ### Chipyard Version and Hash...
It's true that this is an unsual config, but maybe it's worth initiating an issue, I setup a RV64 with usingVM being false, and the firrtl lowering will complain about...
https://github.com/chipsalliance/rocket-chip/blob/69d92c2dedbeaeee325f8f2cf1e7388ad7d4645a/src/main/scala/tilelink/AtomicAutomata.scala#LL244C11-L244C66 I am going through `TLAtomicAutomata` module, and feel confused about the loc above. Should that be `in.d.bits.corrupt := d_cam_corrupt || out.d.bits.corrupt` Also, I wonder if `TLAtomicAutomata ` supports handling...
Hi Team, I am following the instructions in this [FireSim Installation:](https://docs.fires.im/en/1.17.1/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/RHS-Research-Nitefury-II.html#install-vivado-lab-and-cable-drivers:~:text=sudo%20./install_drivers-,4.%20Install%20the%20Xilinx%20XDMA%20and%20XVSEC%20drivers,entry%20for%20each%20FPGA%20you%E2%80%99ve%20added%20to%20the%20Run%20Farm%20Machine.,-6.%20Install%20sshd) step 4 to install the Xilinx XDMA and XVSEC drivers, I followed the instructions and executed following lines of...
### Background Work - [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard) - [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues) - [X] Yes, I searched the [documentation](https://chipyard.readthedocs.io/) ### OS Setup Not-relevant ###...
Hello Community, My team is planing to tapout a chipyard based design, and we have a different Clock Scheme from the default chipyard design: **domain1, **CORE,SBUS,CBUS: 800MHZ**** **domain2, **MBUS,L2Wrapper:400MHZ**** **domain3:...
The RocketTile has servial connections with the context: ``` connectMasterPorts(domain, context) connectSlavePorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) connectInputConstants(domain, context) connectTrace(domain, context) ``` But there is only one `crossingParams.crossingType`...