David O'Connor
David O'Connor
https://github.com/stm32-rs/stm32f3xx-hal/pull/133
Hi. I just implemented DFSDM, and am getting ready to test it on H7 (https://github.com/David-OConnor/stm32-hal/blob/main/src/dfsdm.rs) Which PAC fields are incorrect? Are they still incorrect?
Fix inbound https://github.com/stm32-rs/stm32-rs/pull/637 Offsets only appear to be off for H743 and H743V. Fixing reg names across H7.
HAL limitation. Patch the HAL, or use raw pointers to set the ARR and PSC registers of the timer you're using.
Note that center align modes will also cause incorrect freqs.
As in, some timers use apb1 while others use apb2? Here's how I solved it, where `paste` is a macro crate that lets you build identifiers from parts, `$apb` is...
There are 3 things that affect frequency (or period): PSC register value, ARR register value, and timer clock speed. The current implementation works well for some frequency and clock combos,...
Here's what's going on specifically, as @IamfromSpace pointed out re the overflow: timer clock = 16,000,000. arr = 200 freq = 1 psc = clock / arr / freq =...
Could you clarify what problems being co-prime causes? I've been treating PSC and ARR as interchangeable, which may not be right. (Although it seems to work in practice, so far)
Thank you for the detailed explanation. I've been using timers to fire interrupts and use 50%-duty PWM; this explains why I didn't notice a problem in my tests - and...