David Durst
David Durst
I need to enable a mix of row and column-wise accesses. Currently, all analyses must be fully row-wise or fully column-wise. This is done by blocking.
https://github.com/David-Durst/aetherling/blob/4cc822aa06eae30a01f539524b2b585d6f73f9bc/tests/haskell/test_downsampleStencil.py#L37 The above line of the test takes 3-5 minutes. However, the python file the test is loading the circuit from (https://github.com/David-Durst/aetherling/blob/4cc822aa06eae30a01f539524b2b585d6f73f9bc/tests/haskell/downsampleStencilChain1Per64.py) takes ~10 seconds to generate coreir when the...
There is a bug in both the CoreIR simulator (accessed through magma) and the Verilator simulator (accessed through fault) with an and gate that is receiving mismatched signals. There were...
https://github.com/David-Durst/aetherling/blob/sim_issues/tests/helper_test_readyvalid.py#L54 It would be incredibly helpful if this worked. (in addition to not segfaulting. The segfaulting issue is much more basic, so I made a separate issue for that) I...
https://github.com/David-Durst/aetherling/blob/sim_issues/tests/helper_test_readyvalid.py#L54 This causes CoreIR to segfault and the simulator to stop. This shouldn't be a segfault. Not sure if this is a CoreIR or Magma issue. See https://github.com/rdaly525/coreir/issues/683 for the...
I'm trying to hit 200 MHz on the target FPGA. However, the divs are taking 6ns. See the attached longest paths traces. Are pipelined divs available? [div_long_path.xlsx](https://github.com/rdaly525/coreir/files/3785018/div_long_path.xlsx) (this is moved...
Aetherling testing logs are filled with "/Users/durst/dev/W17-8/coreir/2coreir/src/passes/transform/rungenerators.cpp:10 In Run Generators". There are roughly ~10 per test. It makes it quite challenging to read. How can I disable these prints?
https://github.com/David-Durst/aetherling/blob/sim_issues/tests/helper_test_readyvalid.py#L54 It would be incredibly helpful if this worked. I think this requires changing both Magma and CoreIR.