David Durst

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Note, in order to run this, you'll need the david-ram-tests magma, mantle, aetherling and fault branches (at least as of 6 pm this evening)

Here is CProfile trace of the unit test https://github.com/David-Durst/aetherling/blob/238811583c2cfc8225771f6c5d80cddda3afcea4/tests/haskell/test_downsampleStencil.py#L37. [aetherling_downsample_stencil_chain_performance_log.zip](https://github.com/phanrahan/magma/files/2867965/aetherling_downsample_stencil_chain_performance_log.zip) It takes 7 mins and 47 seconds on a 2017 MBP with a 3.1 GHZ I7 and nothing else running...

In comparison, I am running the much larger tests at https://github.com/David-Durst/aetherling/blob/master/tests/haskell/test_downsampleStencil_big.py in 9 mins and 31 s using fault and verilator. (Note: you need to use https://github.com/David-Durst/fault/tree/aetherling_debugging to run these...

I will not be switching over until I can breakpoint. The tests take multiple minutes to run. I need the ability to stop and look around in a debugger.

https://github.com/David-Durst/aetherling/blob/2043af4641f5bf46f5dd111d0812acf98f4eb932/tests/helper_test_readyvalid.py#L19 has the fault exmaple. @rsetaluri can explain how to get this example running in fault.

@dillonhuff What is the plan for fixing this in the CoreIR simulator?

@dillonhuff here are the coreir and verilog for delayed buffer that was behaving poorly. The issue was that it's CE and WE ports were alternating. [example_bad_delayed_buffer.zip](https://github.com/phanrahan/magma/files/2868020/example_bad_delayed_buffer.zip)

The code at the time of the issue: https://github.com/David-Durst/aetherling/tree/be2105e73d40e4b2168d1492e45a0a5c6f0cc6c6 The commit that fixed the issue: https://github.com/David-Durst/aetherling/commit/8450c2b8beb61008f42633b3212af20c5dbbe489 . This shifted the phase of the inputs to the delayed buffer so that...

https://github.com/phanrahan/magma/issues/352 for matching magma issue