David Tyler

 118 tests left to go, I haven't counted but I think the two cases left are: 1. LDMIA across ROM boundary (maybe just a case of checking when SEQ...

The large number of "2 cycle" failures are because the CPU should have managed to read the timer value _before_ getting blocked by DMA because the code is in IWRAM...

Rough plan to solve the DMA/CPU issue is to properly emulate the bus owner at any given cycle. That means a new flag on the bus and DMA setting/unsetting it...

 Hot _damn_ was that ever really tedious to figure out.


Haven't really done much to specifically pass these but as I fix ppu timing roms and various other roms this one is starting to come together

https://github.com/DaveTCode/GBADotnet/issues/50 shows the last time I was working on this rom and has screenshots showing the background without psychedelics!

Only one I'm correct on is the fast DMA, the others I'm off by at most 1 cycle but in random directions and cases

Tests here are from https://github.com/GhostRain0/PrefetchAbuse

Each column in the test refers to a different wait state configuration: | Column | WaitState | Region 0 | Region 1 | Region 2 | |--------|-----------|----------|----------|----------| | 1 |...