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Dasharo
Rebase dasharo/coreboot to 24.12
Create a new branch, starting from 24.12 release, applying our unmerged commits on top of that.
In the process we might try to squash some related commits - in that case, we should leave some notes there, or in commit message (or both).
We can use this issue as a general discussion of this process.
As for branch naming: we can always rename, we may consider dev/24.12 as we're discussing this flow elsewhere, and perhaps we will adopt some of it in the end.
Additional task, that could be done during rebase: TBD
- patches classification - inspired by: https://docs.yoctoproject.org/contributor-guide/recipe-style-guide.html#patch-upstream-status
- add
Upstream-Statustag to indicate whether the patch isPending(to be submitted upstream), orInappropriate [dasharo-specific](not planned to upstream), or something else - TBD - link to the process description in docs.dasharo
- this process is still in discussion, but we have agreed that some form of classification whether we plan to upstream certain patches, or not, would be useful
I will replace this with link to the actual documentation once in place.
Just an input on my side using 24.12 on which libreboot last release depends on and on which t480 community effort was based on at https://github.com/linuxboot/heads/pull/1906
I foolishly just tried to reuse that branch+patches (and without patches) to build all other old boards and those all fail with messages similar to for buillding x230-hotp-maximized: coreboot-24.12_older_boards_bump.log
Excerpt:
GCC ramstage/libgfxinit/common/dyncpu/hw-gfx-gma-config.o
/home/user/heads/build/x86/coreboot-2412/util/crossgcc/xgcc/bin/i386-elf-gcc --RTS=x230-hotp-maximized/libgnat-x86_32/ -gnatp -Wuninitialized -Wall -Werror -pipe -g -nostdinc -Wstrict-aliasing -Wshadow -fno-common -fomit-frame-pointer -ffunction-sections -fdata-sections -fno-pie -gnatwa.eeD.HHTU.U.W.Y -gnatyN -Os -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -I3rdparty/libgfxinit/common/ -I3rdparty/libgfxinit/common/dyncpu/ -I3rdparty/libgfxinit/common/ironlake/ -I3rdparty/libhwbase/ada/dynamic_mmio/ -I3rdparty/libhwbase/common/ -I3rdparty/libhwbase/common/direct/ -I3rdparty/libhwbase/debug/ -Isrc/console/ -Isrc/drivers/intel/gma/ -Isrc/drivers/intel/gma/hires_fb/ -Isrc/lib/ -Isrc/mainboard/lenovo/x230/variants/x230/ -Ix230-hotp-maximized/libgfxinit/common/ -Ix230-hotp-maximized/libhwbase/common/ -Ix230-hotp-maximized/ramstage/ -D__RAMSTAGE__ -c -o x230-hotp-maximized/ramstage/libgfxinit/common/dyncpu/hw-gfx-gma-config.o 3rdparty/libgfxinit/common/dyncpu/hw-gfx-gma-config.adb
compilation abandoned
{standard input}: Assembler messages:
{standard input}:1: Error: no such instruction: `fatal error,run-time library not installed correctly'
{standard input}:2: Error: no such instruction: `cannot locate file system.ads'
make[1]: *** [Makefile:430: x230-hotp-maximized/ramstage/libgfxinit/common/dyncpu/hw-gfx-gma-config.o] Error 1
make[1]: Leaving directory '/home/user/heads/build/x86/coreboot-2412'
tail /home/user/heads/build/x86/log/coreboot-2412.log
-----
printf " GENERATE libgfxinit/common/hw-gfx-gma-config.ads\n"
GENERATE libgfxinit/common/hw-gfx-gma-config.ads
sed -e's/<<GEN>>/Ironlake/' -e's/<<PCH>>/Cougar_Point/' -e's/<<PANEL_1_PORT>>/LVDS/' -e's/<<PANEL_2_PORT>>/Disabled/' -e's/<<ANALOG_I2C_PORT>>/PCH_DAC/' -e's/<<DEFAULT_MMIO_BASE>>/0 /' -e's/<<IGNORE_STRAPS>>/False/' \
-e'/constant Gen_CPU/d' \
-e's/<genbool>/constant Boolean/' \
-e's/<\(g45\(...\)*\)bool>/<\1var> Boolean/' -e's/<\(ilk\(...\)*\)bool>/<\1var> Boolean/' -e's/<\(hsw\(...\)*\)bool>/<\1var> Boolean/' -e's/<\(skl\(...\)*\)bool>/<\1var> Boolean/' -e's/<\(tgl\(...\)*\)bool>/<\1var> Boolean/' \
-e's/<\(...\)*ilk\(...\)*var>/<cpufunc>/' \
-e's/<g45\(...\)*var>/<cpufunc> /' -e's/<ilk\(...\)*var>/<cpufunc> /' -e's/<hsw\(...\)*var>/<cpufunc> /' -e's/<skl\(...\)*var>/<cpufunc> /' -e's/<tgl\(...\)*var>/<cpufunc> /' \
-e's/\(.*: *<cpufunc>.*:=\) *\(.*\);/\1\n (\2);/' \
-e's/\([^ ][^ ]*\) *: *<cpufunc> *\([^ ]*\) *:=/function \1 return \2 is/' \
-e's/<cpunull>//' \
3rdparty/libgfxinit/common/hw-gfx-gma-config.ads.template >x230-hotp-maximized/libgfxinit/common/hw-gfx-gma-config.ads
GCC ramstage/libgfxinit/common/dyncpu/hw-gfx-gma-config.o
/home/user/heads/build/x86/coreboot-2412/util/crossgcc/xgcc/bin/i386-elf-gcc --RTS=x230-hotp-maximized/libgnat-x86_32/ -gnatp -Wuninitialized -Wall -Werror -pipe -g -nostdinc -Wstrict-aliasing -Wshadow -fno-common -fomit-frame-pointer -ffunction-sections -fdata-sections -fno-pie -gnatwa.eeD.HHTU.U.W.Y -gnatyN -Os -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -I3rdparty/libgfxinit/common/ -I3rdparty/libgfxinit/common/dyncpu/ -I3rdparty/libgfxinit/common/ironlake/ -I3rdparty/libhwbase/ada/dynamic_mmio/ -I3rdparty/libhwbase/common/ -I3rdparty/libhwbase/common/direct/ -I3rdparty/libhwbase/debug/ -Isrc/console/ -Isrc/drivers/intel/gma/ -Isrc/drivers/intel/gma/hires_fb/ -Isrc/lib/ -Isrc/mainboard/lenovo/x230/variants/x230/ -Ix230-hotp-maximized/libgfxinit/common/ -Ix230-hotp-maximized/libhwbase/common/ -Ix230-hotp-maximized/ramstage/ -D__RAMSTAGE__ -c -o x230-hotp-maximized/ramstage/libgfxinit/common/dyncpu/hw-gfx-gma-config.o 3rdparty/libgfxinit/common/dyncpu/hw-gfx-gma-config.adb
compilation abandoned
{standard input}: Assembler messages:
{standard input}:1: Error: no such instruction: `fatal error,run-time library not installed correctly'
{standard input}:2: Error: no such instruction: `cannot locate file system.ads'
make[1]: *** [Makefile:430: x230-hotp-maximized/ramstage/libgfxinit/common/dyncpu/hw-gfx-gma-config.o] Error 1
make[1]: Leaving directory '/home/user/heads/build/x86/coreboot-2412'
make: *** [Makefile:570: /home/user/heads/build/x86/coreboot-2412/x230-hotp-maximized/.build] Error 1
(Meaning Heads cannot use 24.12 without patching it...)
Attaching very much incomplete Dasharo patches review list: https://paste.dasharo.com/?df2a581113227e19#Aao6uQy1VAWBtWhAfHBEXA7uNHBawWzHLTh4v8QjWhMW
and branch: https://github.com/Dasharo/coreboot/commits/pq-test/
I made some review a couple of months ago in a burst of inspiration. Maybe it will be somehow useful, maybe not at all.
Keep in mind that Dasharo EC got merged upstream, so we will need to switch novacustom boards from System76 to Dasharo EC. We also have a lot of patches that weren't sent upstream yet, like the EC update code.
Also note that NovaCustom V5x0TU was sent as novacustom/mtl-h instead of clevo/mtl-h which is how it's currently called in our fork, so we'll need to adapt all patches to the new path :\
I think this is a chance to clean up the Dasharo EC and NovaCustom patches and send as much as possible upstream
@mkopec
I think this is a chance to clean up the Dasharo EC and NovaCustom patches and send as much as possible upstream
Do you want to contribute there?
Also note that NovaCustom V5x0TU was sent as novacustom/mtl-h instead of clevo/mtl-h which is how it's currently called in our fork, so we'll need to adapt all patches to the new path :\
Which naming scheme do we want to commit to stay consistent?
In the process we might try to squash some related commits - in that case, we should leave some notes there, or in commit message (or both).
What kind of notes? Which original commits are being squashed? Non-squashed commits won't have any such references though.
Additional task, that could be done during rebase
Rather after commits are rebased. It doesn't work well to change things while rebasing them.
I foolishly just tried to reuse that branch+patches (and without patches) to build all other old boards and those all fail with messages similar to for buillding x230-hotp-maximized:
Not sure we'll hit that Ada issue.
Also note that NovaCustom V5x0TU was sent as
novacustom/mtl-hinstead ofclevo/mtl-hwhich is how it's currently called in our fork, so we'll need to adapt all patches to the new path :\
Not necessarily. git detects renames well enough provided that files didn't change too much. I even had to suppress this behaviour when rebasing EDK because it found non-existing renames and applied changes to wrong files :)
Attaching very much incomplete Dasharo patches review list:
Thanks, will use after rebasing and on conflicts.
Which naming scheme do we want to commit to stay consistent?
novacustom/mtl-h
Do you want to contribute there?
I meant upstream coreboot, I'm not sure if we have anything worth cotributing to System76 EC, it's mostly board specific changes and fixes / hacks for our own issues
coreboot branch: https://github.com/Dasharo/coreboot/commits/dasharo-24.12/ EDK2 branch: https://github.com/Dasharo/edk2/commits/dasharo-24.12/ dasharo-blobs branch: https://github.com/Dasharo/dasharo-blobs/commits/dasharo-24.12/
All boards build by now https://github.com/Dasharo/coreboot/actions/runs/13477378895.
All of Makefile.inc became Makefile.mk.
Size of EDK's image had to be increased due to 9c15a9b7ae2e in upstream which adds -z common-page-size=0x1000 to linker's invocation to get proper alignment.
coreboot did some updates to FSP headers and I replicated them in dasharo-blobs.
@miczyg1, what about src/mainboard/hardkernel/odroid-h4 and src/mainboard/hardkernel/odroid_h4? The main issue is that their Kconfig options are identically named which breaks the build, as a workaround I removed upstream version, but maybe they can be merged? Not necessarily now, because I doubt it will just work out of the box.
Also note that NovaCustom V5x0TU was sent as novacustom/mtl-h instead of clevo/mtl-h which is how it's currently called in our fork, so we'll need to adapt all patches to the new path :\
Done. In addition to paths BOARD_CLEVO_V* and BOARD_CLEVO_MTLH* were updated as s/CLEVO/NOVACUSTOM/.
Keep in mind that Dasharo EC got merged upstream, so we will need to switch novacustom boards from System76 to Dasharo EC. We also have a lot of patches that weren't sent upstream yet, like the EC update code.
Sounds like local changes in the fork need to be applied to ec/dasharo while doing the switch. Will try that.
@miczyg1, what about
src/mainboard/hardkernel/odroid-h4andsrc/mainboard/hardkernel/odroid_h4? The main issue is that theirKconfigoptions are identically named which breaks the build, as a workaround I removed upstream version, but maybe they can be merged? Not necessarily now, because I doubt it will just work out of the box.
We will have to merge it somehow. Upstream should have a priority (generally). What size of a diff are we talking about here? @SergiiDmytruk
@miczyg1
Kconfig | 69 +++++++++++++++++---------
Kconfig.name | 4 +-
Makefile.mk | 5 ++
acpi/superio.asl | 7 +++
board_info.txt | 16 +++---
bootblock.c | 68 ++++++++++++++++++++------
devicetree.cb | 167 ++++++++++++++++++++++++++++++++++++--------------------------
die.c | 23 +++++++++
dsdt.asl | 5 ++
gpio.c | 609 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
gpio.h | 8 +++
hda_verb.c | 2 +-
mainboard.c | 233 +++++++++-----------------------------------------------------------------------------
romstage_fsp_params.c | 24 ++++++---
vboot-rwa.fmd | 36 ++++++++++++++
15 files changed, 940 insertions(+), 336 deletions(-)
About 400 lines of the difference is caused by GPIO definitions (our 586 lines vs. 198 in upstream; some are due to comments, but not only that). Our bootblock.c doesn't use generic ITE GPIO driver. Other than device tree changes and addition of Vboot on our side, the remaining difference is quite small with some changes being purely stylistic.
full diff
diff --git a/Kconfig b/Kconfig
index 3e03116db75..bbcddfcb797 100644
--- a/Kconfig
+++ b/Kconfig
@@ -1,10 +1,11 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
if BOARD_HARDKERNEL_ODROID_H4
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
+ select SOC_INTEL_ALDERLAKE_PCH_N
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SUPERIO_ITE_IT8613E
select CRB_TPM
select DRIVERS_UART_8250IO
select FSP_TYPE_IOT
@@ -12,30 +13,54 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_INTEL_PTT
select INTEL_GMA_HAVE_VBT
- select SUPERIO_ITE_IT8613E
- select SOC_INTEL_ALDERLAKE_PCH_N
- select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select USE_DDR5
config MAINBOARD_DIR
- default "hardkernel/odroid-h4"
+ default "hardkernel/odroid_h4"
config MAINBOARD_PART_NUMBER
default "ODROID-H4"
-config ODROID_H4_ENABLE_SAGV
- bool "Enable SAGV"
- default y
- help
- SAGV (System Agent GeyserVille) is Intel's implementation of
- DVFS (Dynamic Voltage Frequency Scaling) that reduces energy
- consumption of the SA and DRAM during low-load conditions by
- automatically switching to lower voltages / frequencies when
- the system load is low enough. When enabled, memory training
- has to run multiple times (once per SAGV point), which slows
- down booting (but only when the MRC cache is unusable).
-
- If unsure, keep enabled. If reflashing often, disabling this
- option can be useful to reduce memory training time.
-
-endif #BOARD_HARDKERNEL_ODROID_H4
+config MAINBOARD_VENDOR
+ default "HARDKERNEL"
+
+config MAINBOARD_FAMILY
+ default "Default String"
+
+config DIMM_SPD_SIZE
+ default 1024
+
+config DIMM_MAX
+ default 2
+
+config UART_FOR_CONSOLE
+ default 0
+
+config USE_PM_ACPI_TIMER
+ default n
+
+config CBFS_SIZE
+ default 0xa00000
+
+config VBOOT
+ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+ select GBB_FLAG_DISABLE_FWMP
+ select GBB_FLAG_DISABLE_LID_SHUTDOWN
+ select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+ select VBOOT_ALWAYS_ENABLE_DISPLAY
+ select VBOOT_NO_BOARD_SUPPORT
+ select HAS_RECOVERY_MRC_CACHE
+ select VBOOT_NO_TPM
+ select VBOOT_ENABLE_CBFS_FALLBACK
+ select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE
+
+config VBOOT_SLOTS_RW_A
+ default y if VBOOT
+
+config SOC_INTEL_CSE_SEND_EOP_EARLY
+ default n
+
+config FMDFILE
+ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A
+
+endif
diff --git a/Kconfig.name b/Kconfig.name
index b7a26bc508b..6c276e7145d 100644
--- a/Kconfig.name
+++ b/Kconfig.name
@@ -1,4 +1,2 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
config BOARD_HARDKERNEL_ODROID_H4
- bool "ODROID-H4 / H4+ / H4 Ultra"
+ bool "ODROID H4"
diff --git a/Makefile.mk b/Makefile.mk
index 2e6759f0936..f2bc23054f4 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -2,6 +2,11 @@
bootblock-y += bootblock.c
+romstage-y += gpio.c
romstage-y += romstage_fsp_params.c
ramstage-y += mainboard.c
+ramstage-y += gpio.c
+
+bootblock-y += die.c
+romstage-y += die.c
diff --git a/acpi/superio.asl b/acpi/superio.asl
new file mode 100644
index 00000000000..b7d6a64799d
--- /dev/null
+++ b/acpi/superio.asl
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define IT8613E_SHOW_UARTA
+
+#include <superio/ite/it8613e/acpi/superio.asl>
diff --git a/board_info.txt b/board_info.txt
index e0c5888b97e..23c4523e415 100644
--- a/board_info.txt
+++ b/board_info.txt
@@ -1,9 +1,7 @@
-Vendor name: Hardkernel
-Board name: Odroid H4
-Board URL: https://wiki.odroid.com/odroid-h4/start
-Category: mini
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
-Release year: 2024
+Category: sbc
+Board URL: https://www.hardkernel.com/shop/odroid-h4-plus/
+ROM IC: Winbond W25Q128FW
+ROM package: SOIC8-8
+ROM socketed: no
+Flashrom support: yes
+Release year: 2023
diff --git a/bootblock.c b/bootblock.c
index 31db1352812..fe86cada023 100644
--- a/bootblock.c
+++ b/bootblock.c
@@ -1,32 +1,72 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/io.h>
#include <bootblock_common.h>
+#include <device/pnp_ops.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8613e/it8613e.h>
#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO)
#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1)
+#define ITE_GPIO_BASE 0xa00
+#define ITE_GPIO_PIN(x) (1 << ((x) % 10))
+#define ITE_GPIO_SET(x) (((x) / 10) - 1)
+#define ITE_GPIO_IO_ADDR(x) (ITE_GPIO_BASE + ITE_GPIO_SET(x))
+
+static void ite_set_gpio_iobase(u16 iobase)
+{
+ pnp_enter_conf_state(GPIO_DEV);
+ pnp_set_logical_device(GPIO_DEV);
+ pnp_set_iobase(GPIO_DEV, PNP_IDX_IO1, iobase);
+ pnp_exit_conf_state(GPIO_DEV);
+}
+
+static void ite_gpio_setup(u8 gpio, u8 polarity, u8 pullup, u8 output, u8 enable)
+{
+ u8 set = (gpio / 10) - 1;
+ u8 pin = (gpio % 10);
+
+ /* There are only 6 configurable sets, 8 pins each */
+ if (gpio < 10 || set > 6 || pin > 7)
+ return;
+
+ pnp_enter_conf_state(GPIO_DEV);
+ pnp_set_logical_device(GPIO_DEV);
+ if (set < 5) {
+ pnp_unset_and_set_config(GPIO_DEV, GPIO_REG_ENABLE(set),
+ enable << pin, enable << pin);
+ pnp_unset_and_set_config(GPIO_DEV, GPIO_REG_POLARITY(set),
+ polarity << pin, polarity << pin);
+ }
+ pnp_unset_and_set_config(GPIO_DEV, GPIO_REG_OUTPUT(set), output << pin, output << pin);
+ pnp_unset_and_set_config(GPIO_DEV, GPIO_REG_PULLUP(set), pullup << pin, pullup << pin);
+ pnp_exit_conf_state(GPIO_DEV);
+}
+
void bootblock_mainboard_early_init(void)
{
- /* Set up Super I/O GPIOs, values are dumped from vendor firmware */
+ /* Internal VCC_OK */
+ ite_reg_write(GPIO_DEV, 0x23, 0x40);
+ /* Pin7 as GP23 - USB2_EN */
ite_reg_write(GPIO_DEV, 0x26, 0xfb);
+ /* Pin24 as GPO50 (value of 0 on bit0 is reserved, JP1 strapping)*/
ite_reg_write(GPIO_DEV, 0x29, 0x01);
+ /* K8 power sequence sofyware disabled */
ite_reg_write(GPIO_DEV, 0x2c, 0x41);
+ /* PCICLK 25MHz */
ite_reg_write(GPIO_DEV, 0x2d, 0x02);
- ite_reg_write(GPIO_DEV, 0xbc, 0xc0);
- ite_reg_write(GPIO_DEV, 0xbd, 0x03);
- ite_reg_write(GPIO_DEV, 0xc1, 0x0a);
- ite_reg_write(GPIO_DEV, 0xc8, 0x00);
- ite_reg_write(GPIO_DEV, 0xc9, 0x0a);
- ite_reg_write(GPIO_DEV, 0xda, 0xb0);
- ite_reg_write(GPIO_DEV, 0xdb, 0x44);
-
- ite_delay_pwrgd3(GPIO_DEV);
+ ite_kill_watchdog(GPIO_DEV);
+ /* GP21 - USB3_EN, VBUS power gate for the USB3.x ports */
+ ite_gpio_setup(21, GPIO_POL_NO_INVERT, GPIO_PULLUP_DIS,
+ GPIO_OUTPUT_MODE, GPIO_SIMPLE_IO);
+ /* GP23 - USB2_EN, VBUS power gate for the USB2.x ports */
+ ite_gpio_setup(23, GPIO_POL_NO_INVERT, GPIO_PULLUP_DIS,
+ GPIO_OUTPUT_MODE, GPIO_SIMPLE_IO);
+ ite_set_gpio_iobase(ITE_GPIO_BASE);
+ /* GP21 and GP23 to low to enable USB ports VBUS */
+ outb(inb(ITE_GPIO_IO_ADDR(21)) & ~ITE_GPIO_PIN(21), ITE_GPIO_IO_ADDR(21));
+ outb(inb(ITE_GPIO_IO_ADDR(23)) & ~ITE_GPIO_PIN(23), ITE_GPIO_IO_ADDR(23));
ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
}
-
-void bootblock_mainboard_init(void)
-{
-}
diff --git a/devicetree.cb b/devicetree.cb
index 48f35fd421f..dc6b0442513 100644
--- a/devicetree.cb
+++ b/devicetree.cb
@@ -1,37 +1,43 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
chip soc/intel/alderlake
- register "pmc_gpe0_dw0" = "PMC_GPP_A"
- register "pmc_gpe0_dw1" = "PMC_GPP_R"
- register "pmc_gpe0_dw2" = "PMC_GPD"
+ # FSP configuration
+
+ register "eist_enable" = "1"
- register "sagv" = "CONFIG(ODROID_H4_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled"
+ # Sagv Configuration
+ register "sagv" = "SaGv_Enabled"
+ register "RMT" = "0"
+ register "enable_c6dram" = "1"
- register "enable_c6dram" = "true"
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 80,
+ .fall_time_ns = 110,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 80,
+ .fall_time_ns = 110,
+ },
+ }"
register "tcc_offset" = "10" # TCC of 90C
+ device cpu_cluster 0 on end
device domain 0 on
+ subsystemid 0x8086 0x7270 inherit
device ref igpu on
- register "ddi_portA_config" = "1"
- register "ddi_portB_config" = "1"
+ register "ddi_portA_config" = "1" # HDMI on port A
+ register "ddi_portB_config" = "1" # DP on port B
+ # Fixed DP in TCP0
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
end
- device ref xhci on
- ## Yes, the numbering of the three USB2 ports routed to the EXT_HEAD1
- ## pin header does not correlate with the numbering of the USB2 ports
- ## on the ADL-N SoC. But schematics and lsusb agree with the mapping.
- ##
- ## For onboard USB Type-A ports, tune PHYs for short trace lengths as
- ## the ODROID-H4 is a tiny board (and exact trace length is unknown).
- ##
- ## The USB2 ports on the EXT_HEAD1 pin header are meant to be cabled.
- ## So, have these ports use medium trace length PHY settings instead.
+ device ref xhci on
register "usb2_ports" = "{
#define ODROID_H4_USB2_PORT_REAR { \
@@ -59,45 +65,56 @@ chip soc/intel/alderlake
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
- register "desc" = ""USB3 Type-A (Bottom Right)""
- register "type" = "UPC_TYPE_USB3_A"
+ register "desc" = ""USB2 Type-A Port 2 (USB3_LAN1)""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+ register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
device ref usb2_port1 on end
- device ref usb3_port1 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB3 Type-A (Top Right)""
- register "type" = "UPC_TYPE_USB3_A"
+ register "desc" = ""USB3 Type-A Port 1 (USB3_LAN1)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+ register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
device ref usb2_port2 on end
- device ref usb3_port2 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB2 P7 (EXT_HEAD1)""
- register "type" = "UPC_TYPE_PROPRIETARY"
+ register "desc" = ""USB2 Port 3 (EXT_HEAD1)""
+ register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB2 P5 (EXT_HEAD1)""
- register "type" = "UPC_TYPE_PROPRIETARY"
+ register "desc" = ""USB2 Port 4 (EXT_HEAD1)""
+ register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB2 Type-A (Top Left)""
- register "type" = "UPC_TYPE_A"
+ register "desc" = ""USB2 Type-A Port 5 (USBLAN1)""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))"
+ register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB2 P6 (EXT_HEAD1)""
- register "type" = "UPC_TYPE_PROPRIETARY"
+ register "desc" = ""USB2 Port 6 (EXT_HEAD1)""
+ register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB2 Type-A (Bottom Left)""
- register "type" = "UPC_TYPE_A"
+ register "desc" = ""USB2 Type-A Port 7 (USBLAN1)""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 2))"
+ register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
device ref usb2_port7 on end
end
end
end
end
+
device ref i2c0 on
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
register "common_soc_config.i2c[0]" = "{
@@ -114,69 +131,74 @@ chip soc/intel/alderlake
.fall_time_ns = 110,
}"
end
+ device ref heci1 on end
+ device ref sata on
+ register "sata_salp_support" = "1"
+
+ register "sata_ports_enable" = "{
+ [0] = 0,
+ [1] = 1,
+ }"
+
+ register "sata_ports_hotplug" = "{
+ [0] = 0,
+ [1] = 1,
+ }"
+ end
+
device ref emmc on
register "emmc_enable_hs400_mode" = "true"
end
- device ref pcie_rp3 on # LAN1
+
+ # LAN1 Intel i226
+ device ref pcie_rp3 on
register "pch_pcie_rp[PCH_RP(3)]" = "{
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
.clk_src = 1,
.clk_req = 1,
- .flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
- device ref pcie_rp4 on # LAN2
+ # LAN2 Intel i226
+ device ref pcie_rp4 on
register "pch_pcie_rp[PCH_RP(4)]" = "{
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
.clk_src = 2,
.clk_req = 2,
- .flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
- device ref pcie_rp7 on # ASM1064B SATA
+ # ASMedia PCie to 4xSATA
+ device ref pcie_rp7 on
register "pch_pcie_rp[PCH_RP(7)]" = "{
- .clk_src = 3,
- .clk_req = 3, // Use hardwired CLKREQ# to allow clock gating
.flags = PCIE_RP_LTR | PCIE_RP_AER,
+ .clk_src = 3,
+ .clk_req = 3,
}"
end
- device ref pcie_rp9 on # M.2 M (x4)
+
+ # NVMe x4 link
+ device ref pcie_rp9 on
register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
.clk_src = 0,
.clk_req = 0,
- .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
- }"
+ }"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
"M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X"
end
+
device ref pch_espi on
+ # LPC generic I/O ranges
register "gen1_dec" = "0x00fc0201"
register "gen2_dec" = "0x007c0a01"
register "gen3_dec" = "0x000c03e1"
register "gen4_dec" = "0x001c02e1"
chip superio/ite/it8613e
- register "ec.vin_mask" = "VIN0 | VIN1 | VIN2 | VIN4 | VIN5"
- # TODO: figure out how to make PECI work
- register "TMPIN1.mode" = "THERMAL_DIODE"
- #register "TMPIN1.mode" = "THERMAL_PECI"
- #register "TMPIN1.offset" = "0x56"
- register "FAN2" = "{
- .mode = FAN_SMART_AUTOMATIC,
- .smart = {
- .tmpin = 1,
- .tmp_off = 20,
- .tmp_start = 35,
- .tmp_full = 70,
- .tmp_delta = 1,
- .pwm_start = 20,
- .slope = 3,
- .smoothing = 0,
- },
- }"
-
device pnp 2e.1 on # COM 1
io 0x60 = 0x3f8
irq 0x70 = 4
irq 0xf0 = 0x01
+ irq 0xf1 = 0x52 # IRQ low level
end
device pnp 2e.4 on # Environment Controller
io 0x60 = 0xa30
@@ -194,13 +216,18 @@ chip soc/intel/alderlake
device pnp 2e.a off end # CIR
end
end
+ device ref p2sb hidden end
+ device ref pmc hidden
+ register "pmc_gpe0_dw0" = "PMC_GPP_A"
+ register "pmc_gpe0_dw1" = "PMC_GPP_R"
+ register "pmc_gpe0_dw2" = "PMC_GPD"
+ end
device ref hda on
- register "pch_hda_dsp_enable" = "true"
- register "pch_hda_sdi_enable[0]" = "true"
- register "pch_hda_audio_link_hda_enable" = "true"
- register "pch_hda_idisp_codec_enable" = "true"
- register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
- register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+ register "pch_hda_audio_link_hda_enable" = "1"
+ register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+ register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+ register "pch_hda_idisp_codec_enable" = "true"
+ register "pch_hda_sdi_enable[0]" = "1"
end
device ref smbus on end
diff --git a/die.c b/die.c
new file mode 100644
index 00000000000..85fe2299c79
--- /dev/null
+++ b/die.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <delay.h>
+#include <gpio.h>
+
+void die_notify(void)
+{
+ static uint8_t blink = 0;
+
+ if (ENV_POSTCAR)
+ return;
+
+ /* Make SATA LED blink */
+ gpio_output(GPP_B14, 0);
+
+ while (1) {
+ gpio_set(GPP_B14, blink);
+ blink ^= 1;
+ mdelay(500);
+ }
+}
diff --git a/dsdt.asl b/dsdt.asl
index 584f330cbb1..a6e97c4ceb9 100644
--- a/dsdt.asl
+++ b/dsdt.asl
@@ -22,5 +22,10 @@ DefinitionBlock(
#include <soc/intel/alderlake/acpi/tcss.asl>
}
+ Scope (\_SB.PCI0.LPCB)
+ {
+ #include "acpi/superio.asl"
+ }
+
#include <southbridge/intel/common/acpi/sleepstates.asl>
}
diff --git a/gpio.c b/gpio.c
new file mode 100644
index 00000000000..afe7b3d53c6
--- /dev/null
+++ b/gpio.c
@@ -0,0 +1,609 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <gpio.h>
+
+#include "gpio.h"
+
+#ifndef PAD_CFG_GPIO_BIDIRECT
+#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \
+ PAD_BUF(NO_DISABLE) | val, \
+ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
+#endif
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+ /* ------- GPIO Community 0 ------- */
+
+ /* ------- GPIO Group GPP_B ------- */
+
+ /* GPP_B0 - CORE_VID0 */
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+ /* GPP_B1 - CORE_VID1 */
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+ /* GPP_B2 - VRALERT# */
+ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+ /* GPP_B3 - GPIO */
+ PAD_NC(GPP_B3, NONE),
+ /* GPP_B4 - GPIO */
+ PAD_NC(GPP_B4, NONE),
+ /* GPP_B5 - GPIO */
+ PAD_NC(GPP_B5, NONE),
+ /* GPP_B6 - GPIO */
+ PAD_NC(GPP_B6, NONE),
+ /* GPP_B7 - GPIO */
+ PAD_NC(GPP_B7, NONE),
+ /* GPP_B8 - GPIO EMMC_DET# */
+ PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST),
+ /* GPP_B9 - GPIO */
+ PAD_NC(GPP_B9, NONE),
+ /* GPP_B10 - GPIO */
+ PAD_NC(GPP_B10, NONE),
+ /* GPP_B11 - PMCALERT# */
+ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+ /* GPP_B12 - SLP_S0# */
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ /* GPP_B13 - PLTRST# */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+ /* GPP_B14 - SATA_LED# */
+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF4),
+ /* GPP_B15 - GPIO */
+ PAD_NC(GPP_B15, NONE),
+ /* GPP_B16 - GPIO */
+ PAD_NC(GPP_B16, NONE),
+ /* GPP_B17 - GPIO */
+ PAD_NC(GPP_B17, NONE),
+ /* GPP_B18 - GPIO */
+ PAD_NC(GPP_B18, NONE),
+ /* GPP_B19 - GPIO */
+ PAD_NC(GPP_B19, NONE),
+ /* GPP_B20 - GPIO */
+ PAD_NC(GPP_B20, NONE),
+ /* GPP_B21 - GPIO */
+ PAD_NC(GPP_B21, NONE),
+ /* GPP_B22 - GPIO */
+ PAD_NC(GPP_B22, NONE),
+ /* GPP_B23 - GPIO */
+ PAD_NC(GPP_B23, NONE),
+ /* GPP_B24 - GSPI0_CLK_LOOPBK */
+ PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1),
+ /* GPP_B25 - GSPI1_CLK_LOOPBK */
+ PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1),
+
+ /* ------- GPIO Group GPP_T ------- */
+
+ /* GPP_T0 - GPIO */
+ PAD_NC(GPP_T0, NONE),
+ /* GPP_T1 - GPIO */
+ PAD_NC(GPP_T1, NONE),
+ /* GPP_T2 - GPIO */
+ PAD_NC(GPP_T2, NONE),
+ /* GPP_T3 - GPIO */
+ PAD_NC(GPP_T3, NONE),
+ /* GPP_T4 - GPIO */
+ PAD_NC(GPP_T4, NONE),
+ /* GPP_T5 - GPIO */
+ PAD_NC(GPP_T5, NONE),
+ /* GPP_T6 - GPIO */
+ PAD_NC(GPP_T6, NONE),
+ /* GPP_T7 - GPIO */
+ PAD_NC(GPP_T7, NONE),
+ /* GPP_T8 - GPIO */
+ PAD_NC(GPP_T8, NONE),
+ /* GPP_T9 - GPIO */
+ PAD_NC(GPP_T9, NONE),
+ /* GPP_T10 - GPIO */
+ PAD_NC(GPP_T10, NONE),
+ /* GPP_T11 - GPIO */
+ PAD_NC(GPP_T11, NONE),
+ /* GPP_T12 - GPIO */
+ PAD_NC(GPP_T12, NONE),
+ /* GPP_T13 - GPIO */
+ PAD_NC(GPP_T13, NONE),
+ /* GPP_T14 - GPIO */
+ PAD_NC(GPP_T14, NONE),
+ /* GPP_T15 - GPIO */
+ PAD_NC(GPP_T15, NONE),
+
+ /* ------- GPIO Group GPP_A ------- */
+
+ /* GPP_A0 - ESPI_IO0 */
+ PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+ /* GPP_A1 - ESPI_IO1 */
+ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+ /* GPP_A2 - ESPI_IO2 */
+ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+ /* GPP_A3 - ESPI_IO3 */
+ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+ /* GPP_A4 - ESPI_CS0# */
+ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+ /* GPP_A5 - ESPI_ALERT0# */
+ PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
+ /* GPP_A6 - GPIO */
+ PAD_NC(GPP_A6, NONE),
+ /* GPP_A7 - GPIO */
+ PAD_NC(GPP_A7, NONE),
+ /* GPP_A8 - LAN_DISABLE# */
+ PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP),
+ /* GPP_A9 - ESPI_CLK */
+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+ /* GPP_A10 - ESPI_RESET# */
+ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+ /* GPP_A11 - GPIO */
+ PAD_NC(GPP_A11, NONE),
+ /* GPP_A12 - SATAXPCIE1 */
+ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+ /* GPP_A13 - GPIO */
+ PAD_NC(GPP_A13, NONE),
+ /* GPP_A14 - GPIO */
+ PAD_NC(GPP_A14, NONE),
+ /* GPP_A15 - GPIO */
+ PAD_NC(GPP_A15, NONE),
+ /* GPP_A16 - GPIO */
+ PAD_NC(GPP_A16, NONE),
+ /* GPP_A17 - GPIO */
+ PAD_NC(GPP_A17, NONE),
+ /* GPP_A18 - DDSP_HPDB */
+ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+ /* GPP_A19 - DDSP_HPD1 */
+ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+ /* GPP_A20 - GPIO */
+ PAD_NC(GPP_A20, NONE),
+ /* GPP_A21 - GPIO */
+ PAD_NC(GPP_A21, NONE),
+ /* GPP_A22 - GPIO */
+ PAD_NC(GPP_A22, NONE),
+ /* GPP_A23 - GPIO */
+ PAD_NC(GPP_A23, NONE),
+ /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */
+ PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1),
+
+ /* ------- GPIO Community 1 ------- */
+
+ /* ------- GPIO Group GPP_S ------- */
+
+ /* GPP_S0 - GPIO */
+ PAD_NC(GPP_S0, NONE),
+ /* GPP_S1 - GPIO */
+ PAD_NC(GPP_S1, NONE),
+ /* GPP_S2 - GPIO */
+ PAD_NC(GPP_S2, NONE),
+ /* GPP_S3 - GPIO */
+ PAD_NC(GPP_S3, NONE),
+ /* GPP_S4 - GPIO */
+ PAD_NC(GPP_S4, NONE),
+ /* GPP_S5 - GPIO */
+ PAD_NC(GPP_S5, NONE),
+ /* GPP_S6 - GPIO */
+ PAD_NC(GPP_S6, NONE),
+ /* GPP_S7 - GPIO */
+ PAD_NC(GPP_S7, NONE),
+
+ /* ------- GPIO Group GPP_I ------- */
+
+ /* GPP_I5 - GPIO */
+ PAD_NC(GPP_I5, NONE),
+ /* GPP_I7 - EMMC_CMD */
+ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+ /* GPP_I8 - EMMC_DATA0 */
+ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
+ /* GPP_I9 - EMMC_DATA1 */
+ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
+ /* GPP_I10 - EMMC_DATA2 */
+ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
+ /* GPP_I11 - EMMC_DATA3 */
+ PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
+ /* GPP_I12 - EMMC_DATA4 */
+ PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
+ /* GPP_I13 - EMMC_DATA5 */
+ PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
+ /* GPP_I14 - EMMC_DATA6 */
+ PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
+ /* GPP_I15 - EMMC_DATA7 */
+ PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
+ /* GPP_I16 - EMMC_RCLK */
+ PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
+ /* GPP_I17 - EMMC_CLK */
+ PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
+ /* GPP_I18 - EMMC_RESET# */
+ PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
+
+ /* ------- GPIO Group GPP_H ------- */
+
+ /* GPP_H0 - GPIO */
+ PAD_NC(GPP_H0, NONE),
+ /* GPP_H1 - GPIO */
+ PAD_NC(GPP_H1, NONE),
+ /* GPP_H2 - GPIO */
+ PAD_NC(GPP_H2, NONE),
+ /* GPP_H3 - GPIO */
+ PAD_NC(GPP_H3, NONE),
+ /* GPP_H4 - I2C0_SDA */
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+ /* GPP_H5 - I2C0_SCL */
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+ /* GPP_H6 - I2C1_SDA */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* GPP_H7 - I2C1_SCL */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+ /* GPP_H8 - GPIO */
+ PAD_NC(GPP_H8, NONE),
+ /* GPP_H9 - GPIO */
+ PAD_NC(GPP_H9, NONE),
+ /* GPP_H10 - GPIO */
+ PAD_NC(GPP_H10, NONE),
+ /* GPP_H11 - GPIO */
+ PAD_NC(GPP_H11, NONE),
+ /* GPP_H12 - GPIO */
+ PAD_NC(GPP_H12, NONE),
+ /* GPP_H13 - GPIO */
+ PAD_NC(GPP_H13, NONE),
+ /* GPP_H14 - GPIO */
+ PAD_NC(GPP_H14, NONE),
+ /* GPP_H15 - DDPB_CTRLCLK */
+ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+ /* GPP_H16 - GPIO */
+ PAD_NC(GPP_H16, NONE),
+ /* GPP_H17 - DDPB_CTRLDATA */
+ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+ /* GPP_H18 - PROC_C10_GATE# */
+ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+ /* GPP_H19 - GPIO */
+ PAD_NC(GPP_H19, NONE),
+ /* GPP_H20 - GPIO */
+ PAD_NC(GPP_H20, NONE),
+ /* GPP_H21 - GPIO */
+ PAD_NC(GPP_H21, NONE),
+ /* GPP_H22 - GPIO */
+ PAD_NC(GPP_H22, NONE),
+ /* GPP_H23 - GPIO */
+ PAD_NC(GPP_H23, NONE),
+
+ /* ------- GPIO Group GPP_D ------- */
+
+ /* GPP_D0 - GPIO */
+ PAD_NC(GPP_D0, NONE),
+ /* GPP_D1 - GPIO */
+ PAD_NC(GPP_D1, NONE),
+ /* GPP_D2 - GPIO */
+ PAD_NC(GPP_D2, NONE),
+ /* GPP_D3 - GPIO */
+ PAD_NC(GPP_D3, NONE),
+ /* GPP_D4 - GPIO */
+ PAD_NC(GPP_D4, NONE),
+ /* GPP_D5 - SRCCLKREQ0# to PCIE RP 9 (NVMe) */
+ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+ /* GPP_D6 - SRCCLKREQ1# to PCIE RP 3 (LAN1) */
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+ /* GPP_D7 - SRCCLKREQ2# to PCIE RP 4 (LAN2) */
+ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+ /* GPP_D8 - SRCCLKREQ3# presumably for PCIE RP7, but permanently grounded? */
+ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+ /* GPP_D9 - GPIO */
+ PAD_NC(GPP_D9, NATIVE),
+ /* GPP_D10 - GPIO */
+ PAD_NC(GPP_D10, NATIVE),
+ /* GPP_D11 - GPIO */
+ PAD_NC(GPP_D11, NATIVE),
+ /* GPP_D12 - GPIO */
+ PAD_NC(GPP_D12, NATIVE),
+ /* GPP_D13 - GPIO */
+ PAD_NC(GPP_D13, NONE),
+ /* GPP_D14 - GPIO */
+ PAD_NC(GPP_D14, NONE),
+ /* GPP_D15 - GPIO */
+ PAD_NC(GPP_D15, NONE),
+ /* GPP_D16 - GPIO */
+ PAD_NC(GPP_D16, NONE),
+ /* GPP_D17 - GPIO */
+ PAD_NC(GPP_D17, NONE),
+ /* GPP_D18 - GPIO */
+ PAD_NC(GPP_D18, NONE),
+ /* GPP_D19 - GPIO */
+ PAD_NC(GPP_D19, NONE),
+ /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */
+ PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1),
+
+ /* ------- GPIO Group vGPIO ------- */
+
+ /* GPP_VGPIO_0 - GPIO */
+ PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP),
+ /* GPP_VGPIO_4 - GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI),
+ /* GPP_VGPIO_5 - GPIO */
+ PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI),
+ /* GPP_VGPIO_6 - GPP_VGPIO_6 */
+ PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1),
+ /* GPP_VGPIO_7 - GPP_VGPIO_7 */
+ PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1),
+ /* GPP_VGPIO_8 - GPP_VGPIO_8 */
+ PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1),
+ /* GPP_VGPIO_9 - GPP_VGPIO_9 */
+ PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1),
+ /* GPP_VGPIO_10 - GPP_VGPIO_10 */
+ PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1),
+ /* GPP_VGPIO_11 - GPP_VGPIO_11 */
+ PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1),
+ /* GPP_VGPIO_12 - GPP_VGPIO_12 */
+ PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1),
+ /* GPP_VGPIO_13 - GPP_VGPIO_13 */
+ PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1),
+ /* GPP_VGPIO_18 - GPP_VGPIO_18 */
+ PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1),
+ /* GPP_VGPIO_19 - GPP_VGPIO_19 */
+ PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1),
+ /* GPP_VGPIO_20 - GPP_VGPIO_20 */
+ PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1),
+ /* GPP_VGPIO_21 - GPP_VGPIO_21 */
+ PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1),
+ /* GPP_VGPIO_22 - GPP_VGPIO_22 */
+ PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1),
+ /* GPP_VGPIO_23 - GPP_VGPIO_23 */
+ PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1),
+ /* GPP_VGPIO_24 - GPP_VGPIO_24 */
+ PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1),
+ /* GPP_VGPIO_25 - GPP_VGPIO_25 */
+ PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1),
+ /* GPP_VGPIO_30 - GPP_VGPIO_30 */
+ PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1),
+ /* GPP_VGPIO_31 - GPP_VGPIO_31 */
+ PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1),
+ /* GPP_VGPIO_32 - GPP_VGPIO_32 */
+ PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1),
+ /* GPP_VGPIO_33 - GPP_VGPIO_33 */
+ PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1),
+ /* GPP_VGPIO_34 - GPP_VGPIO_34 */
+ PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+ /* GPP_VGPIO_35 - GPP_VGPIO_35 */
+ PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+ /* GPP_VGPIO_36 - GPP_VGPIO_36 */
+ PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+ /* GPP_VGPIO_37 - GPP_VGPIO_37 */
+ PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
+ /* GPP_VGPIO_THC0 - GPP_VGPIO_THC0 */
+ PAD_CFG_NF(GPP_VGPIO_THC0, NONE, DEEP, NF1),
+ /* GPP_VGPIO_THC1 - GPP_VGPIO_THC1 */
+ PAD_CFG_NF(GPP_VGPIO_THC1, NONE, DEEP, NF1),
+
+ /* ------- GPIO Community 2 ------- */
+
+ /* ------- GPIO Group GPP_GPD ------- */
+
+ /* GPD0 - BATLOW# */
+ PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+ /* GPD1 - ACPRESENT */
+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+ /* GPD2 - GPIO */
+ PAD_NC(GPD2, NONE),
+ /* GPD3 - PWRBTN# */
+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+ /* GPD4 - SLP_S3# */
+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+ /* GPD5 - SLP_S4# */
+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+ /* GPD6 - SLP_A# */
+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+ /* GPD7 - GPIO */
+ PAD_NC(GPD7, NONE),
+ /* GPD8 - SUS_CLK */
+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+ /* GPD9 - SLP_WLAN# */
+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+ /* GPD10 - SLP_S5# */
+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+ /* GPD11 - GPIO */
+ PAD_NC(GPD11, NONE),
+ /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */
+ PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1),
+ /* GPD_SLP_LANB - GPD_SLP_LANB */
+ PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1),
+ /* GPD_SLP_SUSB - GPD_SLP_SUSB */
+ PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1),
+ /* GPD_WAKEB - GPD_WAKEB */
+ PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1),
+ /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */
+ PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1),
+
+ /* ------- GPIO Community 4 ------- */
+
+ /* ------- GPIO Group GPP_C ------- */
+
+ /* GPP_C0 - SMBCLK */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+ /* GPP_C1 - SMBDATA */
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+ /* GPP_C2 - GPIO */
+ PAD_NC(GPP_C2, NONE),
+ /* GPP_C3 - GPIO */
+ PAD_NC(GPP_C3, NONE),
+ /* GPP_C4 - GPIO */
+ PAD_NC(GPP_C4, NONE),
+ /* GPP_C5 - GPIO */
+ PAD_NC(GPP_C5, NONE),
+ /* GPP_C6 - GPIO */
+ PAD_NC(GPP_C6, NONE),
+ /* GPP_C7 - GPIO */
+ PAD_NC(GPP_C7, NONE),
+ /* GPP_C8 - GPIO */
+ PAD_NC(GPP_C8, NONE),
+ /* GPP_C9 - GPIO */
+ PAD_NC(GPP_C9, NONE),
+ /* GPP_C10 - GPIO */
+ PAD_NC(GPP_C10, NONE),
+ /* GPP_C11 - GPIO */
+ PAD_NC(GPP_C11, NONE),
+ /* GPP_C12 - GPIO */
+ PAD_NC(GPP_C12, NONE),
+ /* GPP_C13 - GPIO */
+ PAD_NC(GPP_C13, NONE),
+ /* GPP_C14 - GPIO */
+ PAD_NC(GPP_C14, NONE),
+ /* GPP_C15 - GPIO */
+ PAD_NC(GPP_C15, NONE),
+ /* GPP_C16 - GPIO */
+ PAD_NC(GPP_C16, NONE),
+ /* GPP_C17 - GPIO */
+ PAD_NC(GPP_C17, NONE),
+ /* GPP_C18 - GPIO */
+ PAD_NC(GPP_C18, NONE),
+ /* GPP_C19 - GPIO */
+ PAD_NC(GPP_C19, NONE),
+ /* GPP_C20 - GPIO */
+ PAD_NC(GPP_C20, NONE),
+ /* GPP_C21 - GPIO */
+ PAD_NC(GPP_C21, NONE),
+ /* GPP_C22 - GPIO */
+ PAD_NC(GPP_C22, NONE),
+ /* GPP_C23 - GPIO */
+ PAD_NC(GPP_C23, NONE),
+
+ /* ------- GPIO Group GPP_F ------- */
+
+ /* GPP_F0 - GPIO */
+ PAD_NC(GPP_F0, NONE),
+ /* GPP_F1 - GPIO */
+ PAD_NC(GPP_F1, NONE),
+ /* GPP_F2 - GPIO */
+ PAD_NC(GPP_F2, NONE),
+ /* GPP_F3 - GPIO */
+ PAD_NC(GPP_F3, NONE),
+ /* GPP_F4 - GPIO# */
+ PAD_NC(GPP_F4, NONE),
+ /* GPP_F5 - GPIO */
+ PAD_NC(GPP_F5, NONE),
+ /* GPP_F6 - GPIO */
+ PAD_NC(GPP_F6, NONE),
+ /* GPP_F7 - GPIO */
+ PAD_NC(GPP_F7, NONE),
+ /* GPP_F8 - GPIO */
+ PAD_NC(GPP_F8, NONE),
+ /* GPP_F9 - GPIO */
+ PAD_NC(GPP_F9, NONE),
+ /* GPP_F10 - GPIO */
+ PAD_NC(GPP_F10, NONE),
+ /* GPP_F11 - GPIO */
+ PAD_NC(GPP_F11, NONE),
+ /* GPP_F12 - GPIO */
+ PAD_NC(GPP_F12, NONE),
+ /* GPP_F13 - GPIO */
+ PAD_NC(GPP_F13, NONE),
+ /* GPP_F14 - GPIO */
+ PAD_NC(GPP_F14, NONE),
+ /* GPP_F15 - GPIO */
+ PAD_NC(GPP_F15, NONE),
+ /* GPP_F16 - GPIO */
+ PAD_NC(GPP_F16, NONE),
+ /* GPP_F17 - GPIO */
+ PAD_NC(GPP_F17, NONE),
+ /* GPP_F18 - GPIO */
+ PAD_NC(GPP_F18, NONE),
+ /* GPP_F19 - GPIO */
+ PAD_NC(GPP_F19, NONE),
+ /* GPP_F20 - Reserved */
+ PAD_NC(GPP_F20, NONE),
+ /* GPP_F21 - Reserved */
+ PAD_NC(GPP_F21, NONE),
+ /* GPP_F22 - GPIO */
+ PAD_NC(GPP_F22, NONE),
+ /* GPP_F23 - GPIO */
+ PAD_NC(GPP_F23, NONE),
+ /* GPP_F_CLK_LOOPBK - GPIO */
+ PAD_NC(GPP_F_CLK_LOOPBK, NONE),
+
+ /* ------- GPIO Group GPP_HVCMOS ------- */
+
+ /* GPP_L_BKLTEN - n/a */
+ PAD_NC(GPP_L_BKLTEN, NONE),
+ /* GPP_L_BKLTCTL - n/a */
+ PAD_NC(GPP_L_BKLTCTL, NONE),
+ /* GPP_L_VDDEN - n/a */
+ PAD_NC(GPP_L_VDDEN, NONE),
+ /* GPP_SYS_PWROK - n/a */
+ PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1),
+ /* GPP_SYS_RESETB - n/a */
+ PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1),
+ /* GPP_MLK_RSTB - n/a */
+ PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1),
+
+ /* ------- GPIO Group GPP_E ------- */
+
+ /* GPP_E0 - GPIO */
+ PAD_NC(GPP_E0, NONE),
+ /* GPP_E1 - GPIO */
+ PAD_NC(GPP_E1, NONE),
+ /* GPP_E2 - GPIO */
+ PAD_NC(GPP_E2, NONE),
+ /* GPP_E3 - GPIO */
+ PAD_NC(GPP_E3, NONE),
+ /* GPP_E4 - GPIO */
+ PAD_NC(GPP_E4, NONE),
+ /* GPP_E5 - GPIO */
+ PAD_NC(GPP_E5, NONE),
+ /* GPP_E6 - GPIO */
+ PAD_NC(GPP_E6, NONE),
+ /* GPP_E7 - GPIO */
+ PAD_NC(GPP_E7, NONE),
+ /* GPP_E8 - GPIO */
+ PAD_NC(GPP_E8, NONE),
+ /* GPP_E9 - GPIO */
+ PAD_NC(GPP_E9, NONE),
+ /* GPP_E10 - GPIO */
+ PAD_NC(GPP_E10, NONE),
+ /* GPP_E11 - GPIO */
+ PAD_NC(GPP_E11, NONE),
+ /* GPP_E12 - GPIO */
+ PAD_NC(GPP_E12, NONE),
+ /* GPP_E13 - GPIO */
+ PAD_NC(GPP_E13, NONE),
+ /* GPP_E14 - DDSP_HPDA */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+ /* GPP_E15 - Reserved */
+ PAD_NC(GPP_E15, NONE ),
+ /* GPP_E16 - Connetced to pad 67 in M.2 NVMe slot */
+ PAD_CFG_GPI(GPP_E16, NONE, DEEP),
+ /* GPP_E17 - GPIO */
+ PAD_NC(GPP_E17, NONE),
+ /* GPP_E18 - DDP1_CTRLCLK */
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+ /* GPP_E19 - DDP1_CTRLDATA */
+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+ /* GPP_E20 - GPIO */
+ PAD_NC(GPP_E20, NATIVE),
+ /* GPP_E21 - GPIO */
+ PAD_NC(GPP_E21, NATIVE),
+ /* GPP_E22 - DDPA_CTRLCLK */
+ PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1),
+ /* GPP_E23 - DDPA_CTRLDATA */
+ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+ /* GPP_E_CLK_LOOPBK - GPIO */
+ PAD_NC(GPP_E_CLK_LOOPBK, NONE),
+
+ /* ------- GPIO Community 5 ------- */
+
+ /* ------- GPIO Group GPP_R ------- */
+
+ /* GPP_R0 - HDA_BCLK */
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+ /* GPP_R1 - HDA_SYNC */
+ PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+ /* GPP_R2 - HDA_SDO */
+ PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+ /* GPP_R3 - HDA_SDI0 */
+ PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+ /* GPP_R4 - HDA_RST# */
+ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+ /* GPP_R5 - GPIO */
+ PAD_NC(GPP_R5, NONE),
+ /* GPP_R6 - GPIO */
+ PAD_NC(GPP_R6, NONE),
+ /* GPP_R7 - GPIO */
+ PAD_NC(GPP_R7, NONE)
+};
+
+const struct pad_config *board_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
diff --git a/gpio.h b/gpio.h
new file mode 100644
index 00000000000..e2c63ae0829
--- /dev/null
+++ b/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+const struct pad_config *board_gpio_table(size_t *num);
+
+#endif /* CFG_GPIO_H */
diff --git a/hda_verb.c b/hda_verb.c
index c289cdcecbb..0ac706c8511 100644
--- a/hda_verb.c
+++ b/hda_verb.c
@@ -5,7 +5,7 @@
const u32 cim_verb_data[] = {
0x10ec0897, /* Vendor ID: Realtek ALC897 */
0x10ec0897, /* Subsystem ID */
- 15, /* Number of entries */
+ 16, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x10ec0897),
AZALIA_PIN_CFG(0, 0x11, 0x40000000),
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
diff --git a/mainboard.c b/mainboard.c
index d8cfc8814d7..957d06f61ae 100644
--- a/mainboard.c
+++ b/mainboard.c
@@ -1,219 +1,30 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* SPDX-License-Identifier: GPL-2.0-only */
-#include <gpio.h>
-#include <soc/gpio.h>
+#include <device/device.h>
#include <soc/ramstage.h>
+#include <soc/gpio.h>
+#include <gpio.h>
+#include <string.h>
-/*
- * Pad configuration was derived from schematics, revision 0.1
- * - https://wiki.odroid.com/odroid-h4/hardware#odroid-h4_schematics
- */
-static const struct pad_config gpio_table[] = {
-
- /* ------- GPIO Group GPP_A ------- */
- PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* ESPI_IO0 */
- PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* ESPI_IO1 */
- PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* ESPI_IO2 */
- PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* ESPI_IO3 */
- PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* ESPI_CS# */
- PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* ESPI_ALERT# */
- PAD_NC(GPP_A6, NONE),
- PAD_NC(GPP_A7, NONE),
- PAD_CFG_GPO(GPP_A8, 1, PLTRST), /* LAN_DISABLE# */
- PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* ESPI_CLK */
- PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */
- PAD_NC(GPP_A11, NONE),
- PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* M.2_SSD_PEDET_R */
- PAD_NC(GPP_A13, NONE),
- PAD_NC(GPP_A14, NONE),
- PAD_NC(GPP_A15, NONE),
- PAD_NC(GPP_A16, NONE),
- PAD_NC(GPP_A17, NONE),
- PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDI1_HPD */
- PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* TCP0_HPD */
- PAD_NC(GPP_A20, NONE),
- PAD_NC(GPP_A21, NONE),
- PAD_NC(GPP_A22, NONE),
- PAD_NC(GPP_A23, NONE),
-
- /* ------- GPIO Group GPP_B ------- */
- PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */
- PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */
- PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* VRALERT# */
- PAD_NC(GPP_B3, NONE),
- PAD_NC(GPP_B4, NONE),
- PAD_NC(GPP_B5, NONE),
- PAD_NC(GPP_B6, NONE),
- PAD_NC(GPP_B7, NONE),
- PAD_CFG_GPI(GPP_B8, NONE, DEEP), /* EMMC_DET#_L */
- PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PMCALERT# */
- PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */
- PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PM_PLTRST_N */
- PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF4), /* PCH_SATA_LED# */
- PAD_NC(GPP_B15, NONE),
- PAD_NC(GPP_B16, NONE),
- PAD_NC(GPP_B17, NONE),
- PAD_NC(GPP_B18, NONE),
- PAD_NC(GPP_B23, NONE),
-
- /* ------- GPIO Group GPP_C ------- */
- PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
- PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
- PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), /* SMB_ALERT# */
- PAD_NC(GPP_C3, NONE),
- PAD_NC(GPP_C4, NONE),
- PAD_NC(GPP_C5, NONE),
- PAD_NC(GPP_C6, NONE),
- PAD_NC(GPP_C7, NONE),
-
- /* ------- GPIO Group GPP_D ------- */
- PAD_NC(GPP_D0, NONE),
- PAD_NC(GPP_D1, NONE),
- PAD_NC(GPP_D2, NONE),
- PAD_NC(GPP_D3, NONE),
- PAD_NC(GPP_D4, NONE),
- PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCIE_CLKREQ0_N */
- PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCIE_CLKREQ1_N */
- PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* PCIE_CLKREQ2_N */
- PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* CLKREQ3# but always asserted */
- PAD_NC(GPP_D9, NONE),
- PAD_NC(GPP_D10, NONE),
- PAD_NC(GPP_D11, NONE),
- PAD_NC(GPP_D11, NONE),
- PAD_NC(GPP_D13, NONE),
- PAD_NC(GPP_D14, NONE),
- PAD_NC(GPP_D15, NONE),
- PAD_NC(GPP_D16, NONE),
- PAD_NC(GPP_D17, NONE),
- PAD_NC(GPP_D18, NONE),
- PAD_NC(GPP_D19, NONE),
-
- /* ------- GPIO Group GPP_E ------- */
- PAD_NC(GPP_E0, NONE),
- PAD_NC(GPP_E1, NONE),
- PAD_NC(GPP_E2, NONE),
- PAD_NC(GPP_E3, NONE),
- PAD_NC(GPP_E4, NONE),
- PAD_NC(GPP_E5, NONE),
- PAD_NC(GPP_E6, NONE),
- PAD_NC(GPP_E7, NONE),
- PAD_NC(GPP_E8, NONE),
- PAD_NC(GPP_E9, NONE),
- PAD_NC(GPP_E10, NONE),
- PAD_NC(GPP_E11, NONE),
- PAD_NC(GPP_E12, NONE),
- PAD_NC(GPP_E13, NONE),
- PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI0_HPD */
- PAD_NC(GPP_E15, NONE),
- PAD_NC(GPP_E16, NONE), /* Unknown, goes to M.2 pin 67 (NC) */
- PAD_NC(GPP_E17, NONE),
- PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* TCP0_DDCCLK */
- PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* TCP0_DDCDATA */
- PAD_NC(GPP_E20, NONE),
- PAD_NC(GPP_E21, NONE),
- PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), /* DDI0_DDCCLK */
- PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDI0_DDCDATA */
-
- /* ------- GPIO Group GPP_F ------- */
- PAD_NC(GPP_F0, NONE),
- PAD_NC(GPP_F1, NONE),
- PAD_NC(GPP_F2, NONE),
- PAD_NC(GPP_F3, NONE),
- PAD_NC(GPP_F4, NONE),
- PAD_NC(GPP_F5, NONE),
- PAD_NC(GPP_F6, NONE),
- PAD_NC(GPP_F7, NONE),
- PAD_NC(GPP_F10, NONE),
- PAD_NC(GPP_F11, NONE),
- PAD_NC(GPP_F12, NONE),
- PAD_NC(GPP_F13, NONE),
- PAD_NC(GPP_F14, NONE),
- PAD_NC(GPP_F15, NONE),
- PAD_NC(GPP_F16, NONE),
- PAD_NC(GPP_F17, NONE),
- PAD_NC(GPP_F18, NONE),
- PAD_NC(GPP_F22, NONE),
- PAD_NC(GPP_F23, NONE),
-
- /* ------- GPIO Group GPP_H ------- */
- PAD_NC(GPP_H0, NONE),
- PAD_NC(GPP_H1, NONE),
- PAD_NC(GPP_H2, NONE),
- PAD_NC(GPP_H3, NONE),
- PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* I2C_0_SDA */
- PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* I2C_0_SCL */
- PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C_1_SDA */
- PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C_1_SCL */
- PAD_NC(GPP_H8, NONE),
- PAD_NC(GPP_H9, NONE),
- PAD_NC(GPP_H10, NONE),
- PAD_NC(GPP_H11, NONE),
- PAD_NC(GPP_H12, NONE),
- PAD_NC(GPP_H13, NONE),
- PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDI1_DDCCLK */
- PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDI1_DDCDATA */
- PAD_NC(GPP_H18, NONE),
- PAD_NC(GPP_H19, NONE),
- PAD_NC(GPP_H20, NONE),
- PAD_NC(GPP_H21, NONE),
- PAD_NC(GPP_H22, NONE),
- PAD_NC(GPP_H23, NONE),
-
- /* ------- GPIO Group GPP_I ------- */
- PAD_NC(GPP_I5, NONE),
- PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* EMMC_CMD */
- PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* EMMC_DATA_0 */
- PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* EMMC_DATA_1 */
- PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* EMMC_DATA_2 */
- PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), /* EMMC_DATA_3 */
- PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), /* EMMC_DATA_4 */
- PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), /* EMMC_DATA_5 */
- PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), /* EMMC_DATA_6 */
- PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), /* EMMC_DATA_7 */
- PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), /* EMMC_RCLK */
- PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), /* EMMC_CLK */
- PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), /* EMMC_RESET# */
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm));
+ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
- /* ------- GPIO Group GPP_R ------- */
- PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK_R */
- PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC_R */
- PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), /* HDA_SDO_R */
- PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI_R */
- PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), /* HDA_RST_N */
- PAD_NC(GPP_R5, NONE),
- PAD_NC(GPP_R6, NONE),
- PAD_NC(GPP_R7, NONE),
+ params->PcieRpEnableCpm[2] = 1; // LAN1
+ params->PcieRpEnableCpm[3] = 1; // LAN2
+ params->PcieRpEnableCpm[6] = 1; // ASMedia PCIe to SATA
+ params->PcieRpEnableCpm[8] = 1; // NVMe
- /* ------- GPIO Group GPP_S ------- */
- PAD_NC(GPP_S0, NONE),
- PAD_NC(GPP_S1, NONE),
- PAD_NC(GPP_S2, NONE),
- PAD_NC(GPP_S3, NONE),
- PAD_NC(GPP_S4, NONE),
- PAD_NC(GPP_S5, NONE),
- PAD_NC(GPP_S6, NONE),
- PAD_NC(GPP_S7, NONE),
+ // Max payload 256B
+ memset(params->PcieRpMaxPayload, 1, sizeof(params->PcieRpMaxPayload));
- /* ------- GPIO Group GPP_GPD ------- */
- PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* BATLOW# */
- PAD_CFG_NF(GPD1, NONE, PWROK, NF1), /* ACPRESENT */
- PAD_NC(GPD2, NONE),
- PAD_CFG_NF(GPD3, NONE, PWROK, NF1), /* PM_PWRBTN# */
- PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */
- PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */
- PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */
- PAD_NC(GPD7, NONE),
- PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */
- PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */
- PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */
- PAD_NC(GPD11, NONE),
-};
+ // I2C
+ params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
+ params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
+ params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6
+ params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7
-static void mainboard_init(void *chip_info)
-{
- gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+ params->CnviRfResetPinMux = 0;
+ params->CnviClkreqPinMux = 0;
}
-
-struct chip_operations mainboard_ops = {
- .init = mainboard_init,
-};
diff --git a/romstage_fsp_params.c b/romstage_fsp_params.c
index 549a4bdc347..2fb790d5ee0 100644
--- a/romstage_fsp_params.c
+++ b/romstage_fsp_params.c
@@ -3,23 +3,35 @@
#include <fsp/api.h>
#include <soc/romstage.h>
#include <soc/meminit.h>
+#include <soc/gpio.h>
+
+#include "gpio.h"
static const struct mb_cfg ddr5_mem_config = {
.type = MEM_TYPE_DDR5,
- /* According to DOC #573387 rcomp values no longer have to be provided */
- /* DDR DIMM configuration does not need to set DQ/DQS maps */
.ect = true, /* Early Command Training */
.UserBd = BOARD_TYPE_MOBILE,
- .LpDdrDqDqsReTraining = 1
+ .LpDdrDqDqsReTraining = 1,
};
static const struct mem_spd dimm_module_spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
- .smbus[0] = { .addr_dimm[0] = 0x52, },
+ .smbus = {
+ [0] = {
+ .addr_dimm[0] = 0x52,
+ },
+ },
};
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
- const bool half_populated = true;
- memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated);
+ const struct pad_config *pads;
+ size_t num;
+
+ memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false);
+
+ pads = board_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+
+ memupd->FspmConfig.DmiMaxLinkSpeed = 4;
}
diff --git a/vboot-rwa.fmd b/vboot-rwa.fmd
new file mode 100644
index 00000000000..bfe0e6d73b6
--- /dev/null
+++ b/vboot-rwa.fmd
@@ -0,0 +1,36 @@
+FLASH@0xff000000 16M {
+ SI_ALL 6M {
+ SI_DESC 4K
+ SI_ME 0x413000
+ SI_DEVICEEXT2
+ }
+ SI_BIOS 10M {
+ SMMSTORE(PRESERVE) 256K
+
+ RW_MISC 260K {
+ UNIFIED_MRC_CACHE(PRESERVE) {
+ RECOVERY_MRC_CACHE 128K
+ RW_MRC_CACHE 128K
+ }
+ RW_NVRAM(PRESERVE) 4K
+ }
+
+ BOOTSPLASH(CBFS) 252K
+
+ RW_SECTION_A {
+ VBLOCK_A 64K
+ FW_MAIN_A(CBFS)
+ RW_FWID_A 0x100
+ }
+
+ WP_RO 5M {
+ RO_SECTION {
+ FMAP 2K
+ RO_FRID 0x100
+ RO_FRID_PAD 0x700
+ GBB 12K
+ COREBOOT(CBFS)
+ }
+ }
+ }
+}
Regarding board's Kconfig we should stick with upstream changes, then add our changes starting from config MAINBOARD_VENDOR as they are in the diff.
Regarding GPIOs I would prefer to use ours. GPIOs are pretty much always isolated in separate C file... Not sure why it ended up in mainbaord.c
Definitely we keep our vboot rwa layout.
For the romstage file, we need the GPIOs to be initialized before memory init. WHo knwos what dependencies on GPIOs FSP may have.
In mainboard.c I would keep our mainboard_silicon_init_params function.
In hda_verb.c I don't know why there is a different number of verbs.
Regarding the devicetree, first I would eliminate all lines that are identical but landed in different places. Favor keeping upstream state. AS for the USB, I would keep the PLDs, but use upstream's type (UPC). IT8613 HWMON setting should be removed they won't work anyways on this chip. Then all parts which are only present on Dasahro should be kept.
die.c, dsdt.asl, superio.asl have to use our versions.
The bootblock.c ITE GPIO setup has to be rewritten to use common ITE GPIO setup API.
Thanks, @miczyg1. Commit which adds Dasharo modifications to upstream board is https://github.com/Dasharo/coreboot/commit/cdfe69e906144f6e2d388a67d8f0cfb6538bc068. And here is the reverse comparison (not reversed commit, but difference between Dasharo version and updated upstream version to see what didn't get in):
odroid_h4 -> odroid-h4
diff --git a/Kconfig b/Kconfig
index bbcddfcb797..76831b774b2 100644
--- a/Kconfig
+++ b/Kconfig
@@ -1,11 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
if BOARD_HARDKERNEL_ODROID_H4
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
- select SOC_INTEL_ALDERLAKE_PCH_N
- select SOC_INTEL_COMMON_BLOCK_HDA_VERB
- select SUPERIO_ITE_IT8613E
select CRB_TPM
select DRIVERS_UART_8250IO
select FSP_TYPE_IOT
@@ -13,10 +12,13 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_INTEL_PTT
select INTEL_GMA_HAVE_VBT
+ select SUPERIO_ITE_IT8613E
+ select SOC_INTEL_ALDERLAKE_PCH_N
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select USE_DDR5
config MAINBOARD_DIR
- default "hardkernel/odroid_h4"
+ default "hardkernel/odroid-h4"
config MAINBOARD_PART_NUMBER
default "ODROID-H4"
@@ -25,7 +27,7 @@ config MAINBOARD_VENDOR
default "HARDKERNEL"
config MAINBOARD_FAMILY
- default "Default String"
+ default "H4"
config DIMM_SPD_SIZE
default 1024
@@ -63,4 +65,19 @@ config SOC_INTEL_CSE_SEND_EOP_EARLY
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A
-endif
+config ODROID_H4_ENABLE_SAGV
+ bool "Enable SAGV"
+ default y
+ help
+ SAGV (System Agent GeyserVille) is Intel's implementation of
+ DVFS (Dynamic Voltage Frequency Scaling) that reduces energy
+ consumption of the SA and DRAM during low-load conditions by
+ automatically switching to lower voltages / frequencies when
+ the system load is low enough. When enabled, memory training
+ has to run multiple times (once per SAGV point), which slows
+ down booting (but only when the MRC cache is unusable).
+
+ If unsure, keep enabled. If reflashing often, disabling this
+ option can be useful to reduce memory training time.
+
+endif #BOARD_HARDKERNEL_ODROID_H4
diff --git a/Kconfig.name b/Kconfig.name
index 6c276e7145d..b7a26bc508b 100644
--- a/Kconfig.name
+++ b/Kconfig.name
@@ -1,2 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
config BOARD_HARDKERNEL_ODROID_H4
- bool "ODROID H4"
+ bool "ODROID-H4 / H4+ / H4 Ultra"
diff --git a/Makefile.mk b/Makefile.mk
index f2bc23054f4..6e2926fa3b0 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -2,10 +2,11 @@
bootblock-y += bootblock.c
-romstage-y += gpio.c
romstage-y += romstage_fsp_params.c
ramstage-y += mainboard.c
+
+romstage-y += gpio.c
ramstage-y += gpio.c
bootblock-y += die.c
diff --git a/board_info.txt b/board_info.txt
index 23c4523e415..e0c5888b97e 100644
--- a/board_info.txt
+++ b/board_info.txt
@@ -1,7 +1,9 @@
-Category: sbc
-Board URL: https://www.hardkernel.com/shop/odroid-h4-plus/
-ROM IC: Winbond W25Q128FW
-ROM package: SOIC8-8
-ROM socketed: no
-Flashrom support: yes
-Release year: 2023
+Vendor name: Hardkernel
+Board name: Odroid H4
+Board URL: https://wiki.odroid.com/odroid-h4/start
+Category: mini
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2024
diff --git a/bootblock.c b/bootblock.c
index fe86cada023..0999067b150 100644
--- a/bootblock.c
+++ b/bootblock.c
@@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/io.h>
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <superio/ite/common/ite.h>
+#include <superio/ite/common/ite_gpio.h>
#include <superio/ite/it8613e/it8613e.h>
#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO)
@@ -22,51 +22,46 @@ static void ite_set_gpio_iobase(u16 iobase)
pnp_exit_conf_state(GPIO_DEV);
}
-static void ite_gpio_setup(u8 gpio, u8 polarity, u8 pullup, u8 output, u8 enable)
-{
- u8 set = (gpio / 10) - 1;
- u8 pin = (gpio % 10);
-
- /* There are only 6 configurable sets, 8 pins each */
- if (gpio < 10 || set > 6 || pin > 7)
- return;
-
- pnp_enter_conf_state(GPIO_DEV);
- pnp_set_logical_device(GPIO_DEV);
- if (set < 5) {
- pnp_unset_and_set_config(GPIO_DEV, GPIO_REG_ENABLE(set),
- enable << pin, enable << pin);
- pnp_unset_and_set_config(GPIO_DEV, GPIO_REG_POLARITY(set),
- polarity << pin, polarity << pin);
- }
- pnp_unset_and_set_config(GPIO_DEV, GPIO_REG_OUTPUT(set), output << pin, output << pin);
- pnp_unset_and_set_config(GPIO_DEV, GPIO_REG_PULLUP(set), pullup << pin, pullup << pin);
- pnp_exit_conf_state(GPIO_DEV);
-}
-
void bootblock_mainboard_early_init(void)
{
+ /* Set up Super I/O GPIOs, some values are dumped from vendor firmware */
+
/* Internal VCC_OK */
ite_reg_write(GPIO_DEV, 0x23, 0x40);
/* Pin7 as GP23 - USB2_EN */
ite_reg_write(GPIO_DEV, 0x26, 0xfb);
/* Pin24 as GPO50 (value of 0 on bit0 is reserved, JP1 strapping)*/
ite_reg_write(GPIO_DEV, 0x29, 0x01);
- /* K8 power sequence sofyware disabled */
+ /* K8 power sequence software disabled */
ite_reg_write(GPIO_DEV, 0x2c, 0x41);
/* PCICLK 25MHz */
ite_reg_write(GPIO_DEV, 0x2d, 0x02);
+ ite_reg_write(GPIO_DEV, 0xbc, 0xc0);
+ ite_reg_write(GPIO_DEV, 0xbd, 0x03);
+ ite_reg_write(GPIO_DEV, 0xc1, 0x0a);
+ ite_reg_write(GPIO_DEV, 0xc8, 0x00);
+ ite_reg_write(GPIO_DEV, 0xc9, 0x0a);
+ ite_reg_write(GPIO_DEV, 0xda, 0xb0);
+ ite_reg_write(GPIO_DEV, 0xdb, 0x44);
+
ite_kill_watchdog(GPIO_DEV);
/* GP21 - USB3_EN, VBUS power gate for the USB3.x ports */
- ite_gpio_setup(21, GPIO_POL_NO_INVERT, GPIO_PULLUP_DIS,
- GPIO_OUTPUT_MODE, GPIO_SIMPLE_IO);
+ ite_gpio_setup(GPIO_DEV, 21,
+ ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, ITE_GPIO_CONTROL_DEFAULT);
/* GP23 - USB2_EN, VBUS power gate for the USB2.x ports */
- ite_gpio_setup(23, GPIO_POL_NO_INVERT, GPIO_PULLUP_DIS,
- GPIO_OUTPUT_MODE, GPIO_SIMPLE_IO);
+ ite_gpio_setup(GPIO_DEV, 23,
+ ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, ITE_GPIO_CONTROL_DEFAULT);
+
ite_set_gpio_iobase(ITE_GPIO_BASE);
/* GP21 and GP23 to low to enable USB ports VBUS */
outb(inb(ITE_GPIO_IO_ADDR(21)) & ~ITE_GPIO_PIN(21), ITE_GPIO_IO_ADDR(21));
outb(inb(ITE_GPIO_IO_ADDR(23)) & ~ITE_GPIO_PIN(23), ITE_GPIO_IO_ADDR(23));
+ ite_delay_pwrgd3(GPIO_DEV);
+
ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
}
+
+void bootblock_mainboard_init(void)
+{
+}
diff --git a/devicetree.cb b/devicetree.cb
index dc6b0442513..7829aa0511b 100644
--- a/devicetree.cb
+++ b/devicetree.cb
@@ -1,12 +1,17 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
chip soc/intel/alderlake
- # FSP configuration
+ register "pmc_gpe0_dw0" = "PMC_GPP_A"
+ register "pmc_gpe0_dw1" = "PMC_GPP_R"
+ register "pmc_gpe0_dw2" = "PMC_GPD"
- register "eist_enable" = "1"
+ # FSP configuration
+ register "eist_enable" = "true"
# Sagv Configuration
- register "sagv" = "SaGv_Enabled"
+ register "sagv" = "CONFIG(ODROID_H4_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled"
register "RMT" = "0"
- register "enable_c6dram" = "1"
+ register "enable_c6dram" = "true"
register "common_soc_config" = "{
.i2c[0] = {
@@ -23,7 +28,6 @@ chip soc/intel/alderlake
register "tcc_offset" = "10" # TCC of 90C
- device cpu_cluster 0 on end
device domain 0 on
subsystemid 0x8086 0x7270 inherit
device ref igpu on
@@ -38,6 +42,16 @@ chip soc/intel/alderlake
end
device ref xhci on
+ ## Yes, the numbering of the three USB2 ports routed to the EXT_HEAD1
+ ## pin header does not correlate with the numbering of the USB2 ports
+ ## on the ADL-N SoC. But schematics and lsusb agree with the mapping.
+ ##
+ ## For onboard USB Type-A ports, tune PHYs for short trace lengths as
+ ## the ODROID-H4 is a tiny board (and exact trace length is unknown).
+ ##
+ ## The USB2 ports on the EXT_HEAD1 pin header are meant to be cabled.
+ ## So, have these ports use medium trace length PHY settings instead.
+
register "usb2_ports" = "{
#define ODROID_H4_USB2_PORT_REAR { \
@@ -65,47 +79,49 @@ chip soc/intel/alderlake
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
- register "desc" = ""USB2 Type-A Port 2 (USB3_LAN1)""
- register "type" = "UPC_TYPE_A"
+ register "desc" = ""USB3 Type-A (Bottom Right)""
+ register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))"
register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
device ref usb2_port1 on end
+ device ref usb3_port1 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB3 Type-A Port 1 (USB3_LAN1)""
- register "type" = "UPC_TYPE_USB3_A"
+ register "desc" = ""USB3 Type-A (Top Right)""
+ register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
device ref usb2_port2 on end
+ device ref usb3_port2 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB2 Port 3 (EXT_HEAD1)""
- register "type" = "UPC_TYPE_INTERNAL"
+ register "desc" = ""USB2 P7 (EXT_HEAD1)""
+ register "type" = "UPC_TYPE_PROPRIETARY"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB2 Port 4 (EXT_HEAD1)""
- register "type" = "UPC_TYPE_INTERNAL"
+ register "desc" = ""USB2 P5 (EXT_HEAD1)""
+ register "type" = "UPC_TYPE_PROPRIETARY"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB2 Type-A Port 5 (USBLAN1)""
- register "type" = "UPC_TYPE_A"
+ register "desc" = ""USB2 Type-A (Top Left)""
+ register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))"
register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB2 Port 6 (EXT_HEAD1)""
- register "type" = "UPC_TYPE_INTERNAL"
+ register "desc" = ""USB2 P6 (EXT_HEAD1)""
+ register "type" = "UPC_TYPE_PROPRIETARY"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB2 Type-A Port 7 (USBLAN1)""
- register "type" = "UPC_TYPE_A"
+ register "desc" = ""USB2 Type-A (Bottom Left)""
+ register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 2))"
register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
@@ -150,38 +166,34 @@ chip soc/intel/alderlake
register "emmc_enable_hs400_mode" = "true"
end
- # LAN1 Intel i226
- device ref pcie_rp3 on
+ device ref pcie_rp3 on # LAN1 Intel i226
register "pch_pcie_rp[PCH_RP(3)]" = "{
- .flags = PCIE_RP_LTR | PCIE_RP_AER,
.clk_src = 1,
.clk_req = 1,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
- # LAN2 Intel i226
- device ref pcie_rp4 on
+ device ref pcie_rp4 on # LAN2 Intel i226
register "pch_pcie_rp[PCH_RP(4)]" = "{
- .flags = PCIE_RP_LTR | PCIE_RP_AER,
.clk_src = 2,
.clk_req = 2,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
- # ASMedia PCie to 4xSATA
- device ref pcie_rp7 on
+ device ref pcie_rp7 on # ASM1064B SATA (ASMedia PCie to 4xSATA)
register "pch_pcie_rp[PCH_RP(7)]" = "{
- .flags = PCIE_RP_LTR | PCIE_RP_AER,
.clk_src = 3,
- .clk_req = 3,
+ .clk_req = 3, // Use hardwired CLKREQ# to allow clock gating
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
- # NVMe x4 link
- device ref pcie_rp9 on
+ device ref pcie_rp9 on # M.2 M NVMe (x4)
register "pch_pcie_rp[PCH_RP(9)]" = "{
- .flags = PCIE_RP_LTR | PCIE_RP_AER,
.clk_src = 0,
.clk_req = 0,
- }"
+ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+ }"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
"M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X"
end
@@ -217,17 +229,13 @@ chip soc/intel/alderlake
end
end
device ref p2sb hidden end
- device ref pmc hidden
- register "pmc_gpe0_dw0" = "PMC_GPP_A"
- register "pmc_gpe0_dw1" = "PMC_GPP_R"
- register "pmc_gpe0_dw2" = "PMC_GPD"
- end
device ref hda on
- register "pch_hda_audio_link_hda_enable" = "1"
- register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
- register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
- register "pch_hda_idisp_codec_enable" = "true"
- register "pch_hda_sdi_enable[0]" = "1"
+ register "pch_hda_dsp_enable" = "true"
+ register "pch_hda_sdi_enable[0]" = "true"
+ register "pch_hda_audio_link_hda_enable" = "true"
+ register "pch_hda_idisp_codec_enable" = "true"
+ register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+ register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
end
device ref smbus on end
diff --git a/gpio.h b/gpio.h
index e2c63ae0829..c6f88485c59 100644
--- a/gpio.h
+++ b/gpio.h
@@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef CFG_GPIO_H
-#define CFG_GPIO_H
+#ifndef HARDKERNEL_ODROID_H4_GPIO_H
+#define HARDKERNEL_ODROID_H4_GPIO_H
const struct pad_config *board_gpio_table(size_t *num);
-#endif /* CFG_GPIO_H */
+#endif /* HARDKERNEL_ODROID_H4_GPIO_H */
diff --git a/hda_verb.c b/hda_verb.c
index 0ac706c8511..c289cdcecbb 100644
--- a/hda_verb.c
+++ b/hda_verb.c
@@ -5,7 +5,7 @@
const u32 cim_verb_data[] = {
0x10ec0897, /* Vendor ID: Realtek ALC897 */
0x10ec0897, /* Subsystem ID */
- 16, /* Number of entries */
+ 15, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x10ec0897),
AZALIA_PIN_CFG(0, 0x11, 0x40000000),
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
diff --git a/romstage_fsp_params.c b/romstage_fsp_params.c
index 2fb790d5ee0..7a8b1fc9f48 100644
--- a/romstage_fsp_params.c
+++ b/romstage_fsp_params.c
@@ -9,18 +9,16 @@
static const struct mb_cfg ddr5_mem_config = {
.type = MEM_TYPE_DDR5,
+ /* According to DOC #573387 rcomp values no longer have to be provided */
+ /* DDR DIMM configuration does not need to set DQ/DQS maps */
.ect = true, /* Early Command Training */
.UserBd = BOARD_TYPE_MOBILE,
- .LpDdrDqDqsReTraining = 1,
+ .LpDdrDqDqsReTraining = 1
};
static const struct mem_spd dimm_module_spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
- .smbus = {
- [0] = {
- .addr_dimm[0] = 0x52,
- },
- },
+ .smbus[0] = { .addr_dimm[0] = 0x52, },
};
void mainboard_memory_init_params(FSPM_UPD *memupd)
@@ -28,7 +26,8 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
const struct pad_config *pads;
size_t num;
- memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false);
+ const bool half_populated = true;
+ memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated);
pads = board_gpio_table(&num);
gpio_configure_pads(pads, num);
Also moved changes from system76 to dasharo EC (with commit cleanup) and switched boards to it: https://github.com/dasharo/coreboot/compare/cc8dd6c...09f7ac4ca9123c.
@mkopec, @miczyg1, is thermal.asl needed there (https://github.com/Dasharo/coreboot/commit/ef411995534fa68974a471d0a640bf143ea66abd)? Nothing included it (#include "thermal.asl" added by me, might be wrong), so maybe it's not necessary?
Thanks, @miczyg1. Commit which adds Dasharo modifications to upstream board is Dasharo/coreboot@cdfe69e. And here is the reverse comparison (not reversed commit, but difference between Dasharo version and updated upstream version to see what didn't get in):
odroid_h4 -> odroid-h4 Also moved changes from system76 to dasharo EC (with commit cleanup) and switched boards to it: Dasharo/[email protected].
Looks exactly like I wanted it to look like. Thanks.
@mkopec, @miczyg1, is
thermal.aslneeded there (Dasharo/coreboot@ef41199)? Nothing included it (#include "thermal.asl"added by me, might be wrong), so maybe it's not necessary?
Don't know the answer, but @mkopec should.
Difference between System76 EC on dasharo and Dasharo EC on dasharo-24.12 after doing renames in the latter to get intelligible diff. The changes basically correspond to lines/files dropped in upstream after making a copy of System76 EC, so I guess I didn't introduce any regressions.
diff
ec/Kconfig | 5 --
ec/Makefile.mk | 2 +-
ec/acpi.h | 6 +-
ec/acpi/{s76.asl => dasharo.asl} | 38 ++-----------
ec/acpi/ec.asl | 10 +---
ec/commands.h | 8 +--
ec/{system76_ec.c => dasharo_ec.c} | 113 +++++++++++++++----------------------
ec/smbios.c | 9 ---
ec/system76_ec.h | 28 ---------
9 files changed, 60 insertions(+), 159 deletions(-)
diff --git a/ec/Kconfig b/ec/Kconfig
index 3358fdb3558..67a0d93acc1 100644
--- a/ec/Kconfig
+++ b/ec/Kconfig
@@ -16,11 +16,6 @@ config EC_SYSTEM76_EC_DGPU
bool
default n
-config EC_SYSTEM76_EC_OLED
- depends on EC_SYSTEM76_EC
- bool
- default n
-
config EC_SYSTEM76_EC_UPDATE
depends on EC_SYSTEM76_EC
bool "Update the embedded controller firmware"
diff --git a/ec/Makefile.mk b/ec/Makefile.mk
index ebcabe6e63c..41ebf0656d2 100644
--- a/ec/Makefile.mk
+++ b/ec/Makefile.mk
@@ -7,7 +7,7 @@ all-y += buttons.c
smm-$(CONFIG_DEBUG_SMI) += system76_ec.c
cbfs-files-$(CONFIG_EC_SYSTEM76_EC_UPDATE) += ec.rom
-ec.rom-file :=$(call strip_quotes,$(CONFIG_EC_SYSTEM76_EC_UPDATE_FILE))
+ec.rom-file := $(call strip_quotes,$(CONFIG_EC_SYSTEM76_EC_UPDATE_FILE))
ec.rom-compression := $(CBFS_COMPRESS_FLAG)
ec.rom-type := raw
diff --git a/ec/acpi.h b/ec/acpi.h
index 73be6c66501..a76365381ad 100644
--- a/ec/acpi.h
+++ b/ec/acpi.h
@@ -5,7 +5,7 @@
#include <ec/acpi/ec.h>
-#define SYSTEM76_EC_REG_LSTE 0x03
+#define SYSTEM76_EC_REG_LSTE 0x03
#define SYSTEM76_EC_REG_LSTE_LID_STATE 0x01
#define SYSTEM76_EC_REG_BATTERY_START_THRESHOLD 0xBC
@@ -14,8 +14,8 @@
int system76_ec_get_lid_state(void);
enum bat_threshold_type {
- BAT_THRESHOLD_START,
- BAT_THRESHOLD_STOP
+ BAT_THRESHOLD_START,
+ BAT_THRESHOLD_STOP
};
int system76_ec_get_bat_threshold(enum bat_threshold_type type);
diff --git a/ec/acpi/s76.asl b/ec/acpi/dasharo.asl
similarity index 70%
rename from ec/acpi/s76.asl
rename to ec/acpi/dasharo.asl
index 7488db1ee8e..dca99fbb40e 100644
--- a/ec/acpi/s76.asl
+++ b/ec/acpi/dasharo.asl
@@ -1,25 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-// Notifications:
-// 0x80 - hardware backlight toggle
-// 0x81 - backlight toggle
-// 0x82 - backlight down
-// 0x83 - backlight up
-// 0x84 - backlight color change
-// 0x85 - OLED screen toggle
Device (DASH) {
Name (_HID, "DSHR4543")
Name (_UID, 0)
// Hide the device so that Windows does not warn about a missing driver.
Name (_STA, 0xB)
- Method (RSET, 0, Serialized) {
- Debug = "DASH: RSET"
- SAPL(0)
- }
Method (INIT, 0, Serialized) {
Printf ("DASH: INIT")
- RSET()
If (^^PCI0.LPCB.EC0.ECOK) {
// Set flags to use software control
^^PCI0.LPCB.EC0.ECOS = 2
@@ -31,7 +19,6 @@ Device (DASH) {
Method (FINI, 0, Serialized) {
Printf ("DASH: FINI")
- RSET()
If (^^PCI0.LPCB.EC0.ECOK) {
// Set flags to use hardware control
^^PCI0.LPCB.EC0.ECOS = 1
@@ -41,27 +28,6 @@ Device (DASH) {
}
}
- // Get Airplane LED
- Method (GAPL, 0, Serialized) {
- If (^^PCI0.LPCB.EC0.ECOK) {
- If (^^PCI0.LPCB.EC0.AIRP & 0x40) {
- Return (1)
- }
- }
- Return (0)
- }
-
- // Set Airplane LED
- Method (SAPL, 1, Serialized) {
- If (^^PCI0.LPCB.EC0.ECOK) {
- If (Arg0) {
- ^^PCI0.LPCB.EC0.AIRP |= 0x40
- } Else {
- ^^PCI0.LPCB.EC0.AIRP &= 0xBF
- }
- }
- }
-
// Fan names
Method (NFAN, 0, Serialized) {
Return (Package() {
@@ -85,6 +51,10 @@ Device (DASH) {
Local1 = ^^PCI0.LPCB.EC0.RPM2
}
}
+ If (Local1 != 0) {
+ // 60 * (EC frequency / 120) / 2
+ Local1 = 2156250 / Local1
+ }
Return ((Local1 << 8) | Local0)
}
diff --git a/ec/acpi/ec.asl b/ec/acpi/ec.asl
index 8970efe7117..43e36aaac6a 100644
--- a/ec/acpi/ec.asl
+++ b/ec/acpi/ec.asl
@@ -7,6 +7,7 @@ Scope (\_SB) {
#include "hid.asl"
#include "lid.asl"
#include "s76.asl"
+ #include "thermal.asl"
#include "dtt.asl"
}
@@ -57,9 +58,6 @@ Device (\_SB.PCI0.LPCB.EC0)
// EC is now available
ECOK = Arg1
-
- // Reset System76 Device
- ^^^^DASH.RSET()
}
}
@@ -91,9 +89,6 @@ Device (\_SB.PCI0.LPCB.EC0)
// Notify of changes
Notify(^^^^AC, 0)
Notify(^^^^BAT0, 0)
-
- // Reset System76 Device
- ^^^^DASH.RSET()
}
}
@@ -120,9 +115,6 @@ Device (\_SB.PCI0.LPCB.EC0)
Method (_Q0B, 0, NotSerialized) // Screen Toggle
{
Printf ("EC: Screen Toggle")
-#if CONFIG(EC_SYSTEM76_EC_OLED)
- Notify (^^^^DASH, 0x85)
-#endif // CONFIG(EC_SYSTEM76_EC_OLED)
}
Method (_Q0C, 0, NotSerialized) // Mute
diff --git a/ec/commands.h b/ec/commands.h
index 2f954fa3a76..7efd96048c5 100644
--- a/ec/commands.h
+++ b/ec/commands.h
@@ -47,9 +47,9 @@
// Set fan curve
#define CMD_FAN_CURVE_SET 20
// Get security state
-#define CMD_SECURITY_GET = 21,
+#define CMD_SECURITY_GET 21,
// Set security state
-#define CMD_SECURITY_SET = 22,
+#define CMD_SECURITY_SET 22,
// Set camera enablement
#define CMD_CAMERA_ENABLEMENT_SET 23
// Set WiFi + Bluetooth card enablement
@@ -78,8 +78,8 @@
// Persistent option definitions
enum {
- OPT_POWER_ON_AC = 0,
- NUM_OPTIONS
+ OPT_POWER_ON_AC = 0,
+ NUM_OPTIONS
};
uint8_t system76_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data);
diff --git a/ec/system76_ec.c b/ec/dasharo_ec.c
similarity index 95%
rename from ec/system76_ec.c
rename to ec/dasharo_ec.c
index 1449be2d7e8..455a03c35a5 100644
--- a/ec/system76_ec.c
+++ b/ec/dasharo_ec.c
@@ -11,7 +11,6 @@
#include <timer.h>
#include "acpi.h"
#include "commands.h"
-#include "system76_ec.h"
// This is the command region for System76 EC firmware. It must be
// enabled for LPC in the mainboard.
@@ -43,6 +42,17 @@
#define MAX_WRITE_RETRY 3
+enum ec_update_error {
+ /* AC adapter is not connected. */
+ EC_UPDATE_ERR_NO_AC,
+ /* EC did not jump to scratch ROM */
+ EC_UPDATE_ERR_SCRATCH,
+ /* EC erase failed */
+ EC_UPDATE_ERR_ERASE,
+ /* Programming EC failed */
+ EC_UPDATE_ERR_PROGRAM,
+};
+
static inline uint8_t system76_ec_read(uint8_t addr)
{
return inb(SYSTEM76_EC_BASE + (uint16_t)addr);
@@ -53,40 +63,11 @@ static inline void system76_ec_write(uint8_t addr, uint8_t data)
outb(data, SYSTEM76_EC_BASE + (uint16_t)addr);
}
-void system76_ec_init(void)
-{
- // Clear entire command region
- for (int i = 0; i < SYSTEM76_EC_SIZE; i++)
- system76_ec_write((uint8_t)i, 0);
-}
-
-void system76_ec_flush(void)
-{
- system76_ec_write(REG_CMD, CMD_PRINT);
-
- // Wait for command completion, for up to 10 milliseconds, with a
- // test period of 1 microsecond
- wait_us(SPI_TIMEOUT_10MS, system76_ec_read(REG_CMD) == CMD_FINISHED);
-
- system76_ec_write(CMD_PRINT_REG_LEN, 0);
-}
-
-void system76_ec_print(uint8_t byte)
-{
- uint8_t len = system76_ec_read(CMD_PRINT_REG_LEN);
- system76_ec_write(CMD_PRINT_REG_DATA + len, byte);
- system76_ec_write(CMD_PRINT_REG_LEN, len + 1);
-
- // If we hit the end of the buffer, or were given a newline, flush
- if (byte == '\n' || len >= (SYSTEM76_EC_SIZE - CMD_PRINT_REG_DATA))
- system76_ec_flush();
-}
-
uint8_t system76_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data)
{
int i;
- if (len > SYSTEM76_EC_SIZE - 2) {
+ if (len > SYSTEM76_EC_SIZE - REG_DATA) {
printk(BIOS_ERR, "system76_ec: Invalid command length\n");
return -1;
}
@@ -106,7 +87,39 @@ uint8_t system76_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data)
// test period of 1 microsecond
wait_us(SPI_TIMEOUT_10MS, system76_ec_read(REG_CMD) == CMD_FINISHED);
- return (system76_ec_read(REG_RESULT));
+ return system76_ec_read(REG_RESULT);
+}
+
+int system76_ec_get_bat_threshold(enum bat_threshold_type type)
+{
+ int ret = -1;
+
+ switch (type) {
+ case BAT_THRESHOLD_START:
+ ret = ec_read(SYSTEM76_EC_REG_BATTERY_START_THRESHOLD);
+ break;
+ case BAT_THRESHOLD_STOP:
+ ret = ec_read(SYSTEM76_EC_REG_BATTERY_STOP_THRESHOLD);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+void system76_ec_set_bat_threshold(enum bat_threshold_type type, uint8_t value)
+{
+ switch (type) {
+ case BAT_THRESHOLD_START:
+ ec_write(SYSTEM76_EC_REG_BATTERY_START_THRESHOLD, value);
+ break;
+ case BAT_THRESHOLD_STOP:
+ ec_write(SYSTEM76_EC_REG_BATTERY_STOP_THRESHOLD, value);
+ break;
+ default:
+ break;
+ }
}
uint8_t system76_ec_read_version(uint8_t *data)
@@ -177,38 +190,6 @@ uint8_t system76_ec_read_board(uint8_t *data)
return result;
}
-int system76_ec_get_bat_threshold(enum bat_threshold_type type)
-{
- int ret = -1;
-
- switch (type) {
- case BAT_THRESHOLD_START:
- ret = ec_read(SYSTEM76_EC_REG_BATTERY_START_THRESHOLD);
- break;
- case BAT_THRESHOLD_STOP:
- ret = ec_read(SYSTEM76_EC_REG_BATTERY_STOP_THRESHOLD);
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-void system76_ec_set_bat_threshold(enum bat_threshold_type type, uint8_t value)
-{
- switch (type) {
- case BAT_THRESHOLD_START:
- ec_write(SYSTEM76_EC_REG_BATTERY_START_THRESHOLD, value);
- break;
- case BAT_THRESHOLD_STOP:
- ec_write(SYSTEM76_EC_REG_BATTERY_STOP_THRESHOLD, value);
- break;
- default:
- break;
- }
-}
-
/* Ported from system76_ectool */
static int firmware_str(char *data, int data_len, const char *key, char *dest, int dest_len)
{
@@ -807,7 +788,7 @@ static int ec_spi_image_verify(uint8_t *image, ssize_t image_sz)
return rv;
}
- rv = -memcmp(sector, image + addr, SPI_SECTOR_SIZE);
+ rv = memcmp(sector, image + addr, SPI_SECTOR_SIZE) ? -1 : 0;
if (rv) {
printk(BIOS_ERR, "%s: failed to verify sector, addr 0x%06x\n",
__func__, addr);
@@ -827,7 +808,7 @@ static int ec_spi_image_verify(uint8_t *image, ssize_t image_sz)
goto exit;
}
- rv = -memcmp(sector, image + addr, image_sz % SPI_SECTOR_SIZE);
+ rv = memcmp(sector, image + addr, image_sz % SPI_SECTOR_SIZE) ? -1 : 0;
if (rv) {
printk(BIOS_ERR, "%s: failed to verify last sector, addr 0x%06x size 0x%lx\n",
__func__, addr, image_sz % SPI_SECTOR_SIZE);
diff --git a/ec/smbios.c b/ec/smbios.c
deleted file mode 100644
index e55d5f09656..00000000000
--- a/ec/smbios.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <smbios.h>
-
-smbios_wakeup_type smbios_system_wakeup_type(void)
-{
- // TODO: Read wake source from EC.
- return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
-}
diff --git a/ec/system76_ec.h b/ec/system76_ec.h
deleted file mode 100644
index da582bc4a49..00000000000
--- a/ec/system76_ec.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SYSTEM76_EC_H
-#define SYSTEM76_EC_H
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/*
- * Send a command to the EC. request_data/request_size are the request payload,
- * request_data can be NULL if request_size is 0. reply_data/reply_size are
- * the reply payload, reply_data can be NULL if reply_size is 0.
- */
-bool system76_ec_cmd(uint8_t cmd, const uint8_t *request_data, uint8_t request_size,
- uint8_t *reply_data, uint8_t reply_size);
-
-enum ec_update_error {
- /* AC adapter is not connected. */
- EC_UPDATE_ERR_NO_AC,
- /* EC did not jump to scratch ROM */
- EC_UPDATE_ERR_SCRATCH,
- /* EC erase failed */
- EC_UPDATE_ERR_ERASE,
- /* Programming EC failed */
- EC_UPDATE_ERR_PROGRAM,
-};
-
-#endif
Latest CI: https://github.com/Dasharo/coreboot/actions/runs/13687018957
Rebase notes
* 2f3a7750087 Switch from system76 to dasharo EC
* e323190c978 ec/dasharo/acpi: add DTT Power and Battery participants
* ecab14ce4e8 ec/dasharo/acpi: add D-notifier ACPI field
* 4001267a529 ec/dasharo: apply EC firmware update in ramstage
* 0673d0feecf ec/dasharo/acpi: add touchpad toggle support
* 0f78015f8e9 ec/dasharo/acpi: add thermal.asl
* 34c9694680b 2024-08-08 mb/hardkernel/odroid-h4: add Dasharo modifications (HEAD -> dasharo-24.12) <by Michał Żygowski>
--supersedes 0efbb882a3d, 34e4539d139
* 4c69406dc6c 2025-02-10 mb/clevo/mtl-h/devicetree.cb: Remove smartamp device (HEAD -> dasharo-24.12) <by Michał Kopeć>
* b4e247151ee 2025-02-07 mb/clevo/mtl-h: Add variant-specific power limits <by Michał Kopeć>
* 8dcf04dee44 2025-02-07 mb/clevo/mtl-h/ramstage.c: Set cnvi_wifi_core according to RF option <by Michał Kopeć>
* ef1c663c65c 2025-03-04 configs: bump EDK2 to fix build failure (HEAD -> dasharo-24.12) <by Sergii Dmytruk>
* ed59b7cf0a2 2025-03-03 payloads,config: Make the quiet and fast boot opt-in <by Michał Żygowski>
--squashed into 053ffd44c82 5d1abc92b6c
* 4b2637c89da 2025-02-28 configs/config.protectli_vp2420: Bump to v1.2.1-rc8 <by Michał Żygowski>
* cb58dfaafc5 2025-02-28 3rdparty/intel-microcode: Bump submodule to microcode-20250211 <by Michał Żygowski>
* 053ffd44c82 2025-02-28 configs/config.protectli: Hide quiet and fast boot optons <by Michał Żygowski>
--squashed with ed59b7cf0a2
--changed title to "configs/config.protectli: bump EDK to control visibility of quiet and fast boot opts"
* 5d1abc92b6c 2025-02-28 payloads/external/edk2: Add Kconfig options to hide quiet and fast boot <by Michał Żygowski>
--squashed with ed59b7cf0a2
* 599f2ce7c6f 2025-02-28 configs/config.protectli_vp2430: Bump to v0.9.0-rc3 <by Michał Żygowski>
* 0feaa7e1844 2025-02-25 ec/s76/ec/acpi/battery.asl: Get battery status directly from EC (HEAD -> dasharo-24.12) <by Wiktor Mowinski>
* 68ef4f3c8d0 2025-02-28 configs: bump EDK2 to fix build failure (HEAD -> dasharo-24.12) <by Sergii Dmytruk>
* e9bc44df5b8 2025-02-28 3rdparty/dasharo-blobs: bump for rebase onto 24.12 <by Sergii Dmytruk>
* dc2d85e4d93 2025-02-27 configs/config.protectli_vp2430: Bump to v0.9.0 <by Michał Żygowski>
* 1a55aad2ce8 2025-02-26 configs/config.protectli_vp32xx: Bump to v0.9.0-rc9 <by Michał Żygowski>
* 838065ff2bb 2025-02-26 configs/config.protectli_vp2420: Bump to v1.2.1-rc7 <by Michał Żygowski>
* 4f430797ef4 2025-02-26 configs/config.protectli_vp2430: Fix broken option <by Michał Żygowski>
--squashed into 90d8f164a54
* eab222aed24 2025-02-26 configs/config.protectli_vp2430: Disable fan curves and efivar option backed <by Michał Żygowski>
* 62f89978dd0 2025-02-26 payloads/external/iPXE/Kconfig: Use proper default for IPXE_SERIAL_CONSOLE <by Michał Żygowski>
* d49cd9eda0a 2025-02-21 configs/config.protectli_vp2420: Bump to v1.2.1-rc6 <by Michał Żygowski>
* 990bd59d42e 2025-02-07 configs/config.protectli_vp32xx: Bump to v0.9.0-rc8 <by Michał Żygowski>
* f0018c0e368 2025-02-07 configs/config.protectli_vp2420: Bump to v1.2.1-rc5 <by Michał Żygowski>
* e5c6acba6ee 2025-02-07 payloads/external/edk2/Kconfig: Do not include Shell by default <by Michał Żygowski>
* 90d8f164a54 2025-02-07 configs: Update edk2 revision so it can build without Shell <by Michał Żygowski>
--squashed with 4f430797ef4
* 4533bbd7f37 2025-02-26 PXE network interface added for Clevo mainboard V5X0TU <by Mateusz Maciejewski>
* f708c04661c 2025-02-25 iPXE: Native support for i218 MTL removed. <by Mateusz Maciejewski>
* 8a53da6e06d 2025-02-26 3rdparty/dasharo-blobs: bump for TGL + ADL GOP <by Michał Kopeć>
* 434721ea51c 2025-02-21 configs/config.novacustom_*: enable HDMI output in firmware <by Filip Lewiński>
* 496bbc932fc 2025-02-20 configs/config.novacustom_v5*0tu: add EDK2_USE_LAPTOP_LID_LIB <by Filip Lewiński>
* 75134ab237d 2025-02-20 payloads/external/edk2/Makefile: fix typo <by Filip Lewiński>
--squashed into 790f55c2ba7
* ee06d88cb20 2024-05-31 soc/common/smbus: Support reading SPD5 hubs for DDR5 <by Jeremy Soller>
--squashed into 188a4127b68
* 37cb3b2deae 2025-02-10 configs/config.dell_optiplex_9010_sff*: remove CONFIG_OPTION_BACKEND_NONE (HEAD -> coreboot, dasharo/dasharo, dasharo/HEAD) <by Filip Lewiński>
* 26042ab0434 2025-01-31 build.sh: build_optiplex_9010: move fw flavor left of version <by Filip Lewiński>
--squash into 2d68a9b8a41
* fd316f583e8 2024-12-16 configs/config.dell_optiplex_9010_sff{_txt}: Disable CMOS option backend <by Filip Lewiński>
* 2203c0e8187 2024-12-12 configs/config.dell_optiplex_9010_sff{_txt}: add iPXE, bump to rc2 <by Filip Lewiński>
* 2d68a9b8a41 2024-12-09 build.sh: correct FW_VERSION parsing for OptiPlex SeaBIOS/UEFI <by Filip Lewiński>
--squashed with 26042ab0434
--TODO: probably squash into dc568a20ee6
* a9ae4f48635 2024-12-06 src/mainboard/dell/snb_ivb_workstations/Kconfig: migrate FMDFILE option to Kconfig from defconfigs <by Filip Lewiński>
* efc381adf2e 2024-11-27 configs/config.dell_optiplex_9010_sff{_txt}: update option order <by Filip Lewiński>
--squashed into fb5aad7cf20
* dc568a20ee6 2024-11-27 build.sh: add options for OptiPlex SeaBIOS/UEFI <by Filip Lewiński>
* fb5aad7cf20 2024-11-06 configs/config.dell_optiplex_9010_sff{_txt}: disable top-down alloc. <by Filip Lewiński>
--squashed with efc381adf2e
* 81dc2f3b276 2025-02-04 configs/config.protectli: Bump edk2 rev to fix throttling temperature (tag: protectli_vault_adln_v0.9.0-rc7, dasharo) <by Michał Żygowski>
* 13252a9e007 2025-02-04 configs/config.protectli_vp32xx: Bump to v0.9.0-rc7 <by Michał Żygowski>
* 7000ed66ab7 2024-12-16 configs/config.novacustom: Enable CBFS Serial Number and UUID <by Michał Żygowski>
* 82b9feadb9e 2024-12-16 configs/config.novacustom: Fix iPXE and edk2 options <by Michał Żygowski>
* 001d6f7702a 2025-01-17 configs/config.protectli_vp2410: Bump to v1.1.1 (tag: protectli_vault_glk_v1.1.1) <by Michał Żygowski>
* 67e5d45d61f 2025-01-17 configs/config.protectli_vp2420: Bump to v1.2.1-rc4 (tag: protectli_vault_ehl_v1.2.1-rc4) <by Michał Żygowski>
* 225d907a33e 2025-01-17 configs/config.protectli_vp66xx: Bump to v0.9.1 (tag: protectli_vault_adl_v0.9.1) <by Michał Żygowski>
* 44edcb5d37c 2025-01-17 configs/config.protectli_vp2420: Fix decompressing custom boot logo <by Michał Żygowski>
* d00a33acf50 2025-01-17 configs/config.protectli_: Bump edk2 revision to fix CPU threshold in menu <by Michał Żygowski>
* 048ca832325 2025-01-15 mb/clevo/mtl-h/variants/igpu/data.vbt: Disable secondary display feature <by Michał Kopeć>
--squashed into 8aa50634892
* d8b24529249 2024-08-13 vc/wuffs: upgrade to Wuffs 0.4.0-alpha.8 <by Nigel Tao>
* 21058cb21a5 2024-08-13 lib/jpeg: avoid calling malloc and free <by Nigel Tao>
* d047598fdf4 2025-01-10 soc/intel/mtl: move IOE P2SB BAR below 4G <by Michał Kopeć>
* 40e8d1a9b99 2025-01-09 mb/clevo/mtl-h: Set MMIO size to 2.5GB <by Michał Kopeć>
--squashed into 8aa50634892
* 5a313c76af2 2025-01-16 soc/intel/cmn/blk/cse/cse.c: ensure resources are allocated <4G <by Michał Kopeć>
* c4edf103987 2025-01-08 soc/intel/cmn/blk/i2c: ensure resources are allocated <4G <by Michał Kopeć>
* b890d38d0f1 2025-01-08 soc/intel/cmn/blk/graphics: ensure framebuffer is allocated <4G <by Michał Kopeć>
* 3138e53472b 2024-12-19 Makefile.mk: Always pull FSP submodule <by Michał Kopeć>
* 8d960e94b73 2024-12-18 soc/intel/cmn/blk/cse/cse.c: skip me_enable while ME is in Debug mode <by Michał Kopeć>
* 9f5143b0f95 2024-12-10 clevo/mtl-h/ramstage.c: implement sleep mode option <by Michał Kopeć>
* 092267f37df 2024-12-10 soc/intel/mtl/fsp_params.c: wire up sleep mode option <by Michał Kopeć>
* a4f9bd2d8c1 2024-11-23 soc/intel/lockdown: Allow locking down SPI and LPC in SMM <by Michał Żygowski>
--no changes to src/soc/intel/xeon_sp/lockdown.c because of afc49fa01317190c0ffe480967ee89243d419777 (was a duplication)
* 9443006a1ae 2024-04-25 soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP <by Shuo Liu>
* e8a3f7e0ea4 2024-11-14 vc/intel/fsp/fsp2_0/iot/meteorlake: add missing MemInfoHob from client vc dir <by Michał Kopeć>
* 4e2fa994b41 2025-01-13 configs/config.protectli_vp2420: Remove Intel ME menu and bump to v1.2.1-rc3 (tag: protectli_vault_ehl_v1.2.1-rc3) <by Michał Żygowski>
* 20fe2a864c8 2025-01-09 configs/config.protectli_vp2420: bump to v1.2.1-rc2 (tag: protectli_vault_ehl_v1.2.1-rc2) <by Michał Żygowski>
* 19f7ae12cc5 2025-01-09 configs/config.protectli_vp2410: bump to v1.1.1-rc3 (tag: protectli_vault_glk_v1.1.1-rc3) <by Michał Żygowski>
* 2c7c8c1e560 2025-01-09 mb/protectli/vault_glk: Program ITE EC to respect SB power option <by Michał Żygowski>
--squashed into dab41d06c03
* d3ade4a8e39 2025-01-09 mb/protectli/vault_ehl: Program ITE EC to respect SB power option <by Michał Żygowski>
* 6233d0e1522 2024-11-14 configs: msi release v1.1.4 and v0.9.2 <by Maciej Pijanowski>
* 08e00a244b5 2024-11-04 configs/config.msi_*: v1.1.4-rc3 and v0.9.2-rc3 <by Sergii Dmytruk>
* 4b661c95426 2024-02-08 src/mainboard/msi: Enable dual TPM <by Michał Żygowski>
* b9823666cdb 2024-10-24 configs/config.msi_*: v1.1.4-rc2 and v0.9.2-rc2 <by Sergii Dmytruk>
* 2292d583d2e 2024-10-16 .github/workflows/build.yml: build capsules for MSI <by Sergii Dmytruk>
* feb963bf812 2024-10-16 configs/config.msi_*: disable iPXE serial console <by Sergii Dmytruk>
* d5b7e46aec9 2024-09-27 configs/config.msi_*: v1.1.4-rc1 and v0.9.2-rc1 <by Sergii Dmytruk>
* fb1706f6f43 2024-09-27 configs/config.msi_*: v1.1.4-rc0 and v0.9.2-rc0 <by Sergii Dmytruk>
* c2a22e9e9e9 2024-10-08 soc/alderlake/Makefile.mk: use microcode from dasharo-blobs <by Sergii Dmytruk>
* 2980666e6a5 2024-10-07 .github: check capsule configuration in defconfigs <by Sergii Dmytruk>
* 57b56b628dd 2024-10-03 configs/config.msi_*: enable CPU configuration menu <by Sergii Dmytruk>
* c44c9d4bebf 2024-09-27 configs/config.msi_ms7e06_*: add CONFIG_OPTION_BACKEND_NONE=y <by Sergii Dmytruk>
* f66a86876a5 2024-09-24 soc/intel/fast_spi/mmap_boot.c: allow mapping whole flash <by Sergii Dmytruk>
* 33e2e1a4718 2024-08-14 capsule.sh: add script for working with capsules <by Sergii Dmytruk>
* f9b4f290d24 2024-07-20 payloads/external/edk2: configure capsule updates <by Sergii Dmytruk>
* 25427362a80 2024-06-28 Documentation/drivers/smmstorev2.md: describe capsule update API <by Krystian Hebel>
* 9bc3dc3f189 2024-06-27 drivers/smmstore: add logic to disable capsule update handling code <by Krystian Hebel>
* ebafbd15f2c 2024-06-26 drivers/smmstore: add ability to write to whole flash <by Krystian Hebel>
* c4e9e60a639 2024-10-02 configs/config.emulation_qemu_x86_q35_uefi: enable capsules <by Krystian Hebel>
* 76391b3866a 2024-06-14 configs/config.msi_*: enable UEFI capsule updates <by Sergii Dmytruk>
* b11c760954d 2024-05-06 dasharo/uefi_capsules.c: coalesce and store UEFI capsules <by Sergii Dmytruk>
* e0147e1317a 2024-06-24 drivers/efi: add optional ESRT-friendly coreboot table tag <by Sergii Dmytruk>
* 68fbc027e52 2024-06-24 configs: bump EDK2 for UEFI capsules support <by Sergii Dmytruk>
* 5488a40f2d4 2024-12-19 configs/config.protectli_vp2410: Fix iPXE serial console and bump to rc2 (tag: protectli_vault_glk_v1.1.1-rc2) <by Michał Żygowski>
* fc085fb1237 2024-12-18 configs/config.protectli_vp2420: Enable features for v1.2.1-rc1 (tag: protectli_vault_ehl_v1.2.1-rc1) <by Michał Żygowski>
* 7d9e8dac1ec 2024-12-18 configs/config.protectli_vp2410: Enable features for v1.1.1-rc1 (tag: protectli_vault_glk_v1.1.1-rc1) <by Michał Żygowski>
* fe2d55d7c99 2024-12-18 configs/config.protectli_vp66xx: Enable features for v0.9.1-rc1 (tag: protectli_vault_adl_v0.9.1-rc1) <by Michał Żygowski>
* cd3f7f7cb33 2024-12-18 .github/workflows/deploy-template.yml: Handle released_by_3mdeb flag correctly <by Michał Żygowski>
--squashed into fa704d3ca9c
* bdf2cb51b6e 2024-12-17 .github/workflows/build.yml: Pass artifact names to Protectli ADL-N deploy (tag: protectli_vp2430_v0.9.0-rc2) <by Michał Żygowski>
--squashed with 89e9705cc4e d904b46b78d 50926bd90a5
* 894da35a815 2024-12-17 configs/config.protectli_vp2430: Bump to v0.9.0-rc2 <by Michał Żygowski>
* fed8b0aa02b 2024-12-12 configs/config.protectli: Bump edk2 for correct TPM PPI <by Michał Żygowski>
* 2dab83ad520 2024-12-12 payloads/external/edk2: Add option to use UEFI variable-backed TPM PPI <by Michał Żygowski>
* d55259698fd 2024-12-12 3rdparty/dasharo-blobs: Bump for Protectli ADL power cycling issue <by Michał Żygowski>
* eabe888c538 2024-11-29 soc/intel/elkhartlake,meteorlake: Disable HECI if ME in debug or disabled mode <by Michał Żygowski>
* d049ccf8f2a 2024-11-26 config.protectli_vp46xx: Add Dasharo ME Options <by Filip Gołaś>
* 55a599910ca 2024-11-26 config.protectli_vp32xx: Add Dasharo ME Options <by Filip Gołaś>
* b40a8956ce8 2024-11-26 config.protectli_vp2420: Add Dasharo ME options <by Filip Gołaś>
* 2dd0da27a98 2024-11-26 config.protectli_vault_jsl_v1x1x: Add Dasharo ME Options <by Filip Gołaś>
* 335c8350846 2024-11-26 soc/intel/jasperlake/Kconfig: select HAVE_INTEL_ME_HAP <by Filip Gołaś>
* f5b2cd54909 2024-11-26 soc/intel/elkhartlake/Kconfig: select HAVE_INTEL_ME_HAP <by Filip Gołaś>
* 2ece2d3f2f0 2024-11-26 soc/intel/cannonlake/Kconfig: select HAVE_INTEL_ME_HAP <by Filip Gołaś>
* f269b7d8b60 2024-11-26 intelblocks/me_16.h: Add Alder Lake-N HAP offsets <by Filip Gołaś>
--squashed into 2cfb4f403b7
* 4b0ea3984f6 2024-11-26 intelblocks/me_13.h: Add Jasper Lake HAP offsets <by Filip Gołaś>
* 46279893000 2024-11-26 intelblocks/me_12.h: Add Comet Lake HAP offsets <by Filip Gołaś>
* a2089debe72 2024-12-11 configs/config.protectli_vp32xx: Revert password policy change and bump to rc6 <by Michał Żygowski>
* 6f1f0373a57 2024-12-09 configs/config.protectli_vp32xx: Bump version ot v0.9.0-rc5 <by Michał Żygowski>
* d9bb5e51da9 2024-12-09 configs/config.protectli_vp2430: Apply same fixes as for VP32xx <by Michał Żygowski>
* 24d4f6d1dc3 2024-12-09 configs/config.protectli_vp32xx: Let JPWR1 control power state after AC loss <by Michał Żygowski>
* ffa0d800239 2024-12-09 configs/config.protectli_vp32xx: Update edk2 to address rc4 issues <by Michał Żygowski>
* fa704d3ca9c 2024-11-27 .github/workflows: add released_by_3mdeb flag (tag: hardkernel_odroid_h4_v0.9.0-rc3) <by Maciej Pijanowski>
--squashed with cd3f7f7cb33
* 50926bd90a5 2024-10-01 .github/workflows: Simplify deploy-template workflow <by Pawel Langowski>
--squashed with 69e5eea4a2d bdf2cb51b6e
* 69e5eea4a2d 2024-10-01 .github/workflows/deploy-template.yml: wip - simplify the deply template <by Maciej Pijanowski>
--squashed into 50926bd90a5
* 1287f8a5c87 2024-09-30 build.sh: Bump SDKVER to 2024-02-18_732134932b <by Michał Żygowski>
* 8c97532ba61 2024-09-30 build.sh: Add DOROID H4 build <by Michał Żygowski>
* 56b50c1e3e2 2024-09-30 .github/workflows/deploy-template.yml: Fix paths for 3mdeb releases <by Michał Żygowski>
--squashed into ec8f9d321d0, ff68728477a
* cb34e77d7d1 2024-09-30 .github/workflows/deploy-template.yml: create board dir structure <by Maciej Pijanowski>
* ec8f9d321d0 2024-09-24 .github/workflows/deploy-template.yml: Add deployment for ODROID H4 <by Michał Żygowski>
--squashed with 56b50c1e3e2
* f2002e32e3e 2024-12-10 configs/config.hardkernel_odroid_h4: Bump to rc3 <by Michał Żygowski>
* 4554ffc4c44 2024-12-05 mb/protecti/vault_adl_n: Use FSP to program AUX bias pads <by Michał Żygowski>
* ec14284b603 2024-12-03 src/mainboard/protectli/vault_adl_n/devicetree.cb: Add PMC mux definitions <by Michał Żygowski>
--squashed into d9f08f95e80
* f57029cf2c0 2024-12-05 configs/config.protectli: Bump edk2 to use variable-backed TPM PPI <by Michał Żygowski>
* 8bff12cee3d 2024-11-27 src/mainboard/protectli/vault_adl_n/acpi/usb_pd.asl: Add missing IRQ <by Michał Żygowski>
--squashed into 503681fe5ba
* 9385f24a75a 2024-12-03 .github/workflows/build.yml: build mtl dgpu EC FW <by Michał Kopeć>
* 82bf2f8f53e 2024-12-03 Revert ".github/workflows/build.yml: temporarily disable EC building" <by Michał Kopeć>
--cancelled out 6c7f0f67197
* 2742fdda142 2024-12-03 Revert "configs/config.novacustom_n*: disable EC update" <by Michał Kopeć>
--cancelled out 0678feaf688
* 1375f4f9025 2024-11-04 mainboard/clevo/adl-p: Enable PCH UART <by Michał Żygowski>
--squash into 1c9034a509c
* 50c5051305f 2024-10-28 mb/clevo/mtl-h: Enable PCH UART debug <by Michał Żygowski>
* ff77a70c9f6 2024-10-23 ec/system76/ec/system76_ec.c: Rework EC FW sync <by Michał Żygowski>
--obsoleted by 4001267a529
* 4fed2c5af9d 2024-11-29 configs/config.protectli: Show Fan Off option <by Michał Żygowski>
* 070cce5ad85 2024-11-29 payloads/external/edk2: Add option to show Fan Off option <by Michał Żygowski>
* ba8d1f8a5ca 2024-11-28 configs/config.protectli_vp32xx: Enable fan control and use Protectli logo <by Michał Żygowski>
* a9d0e152ec0 2024-11-28 configs/config.protectli_vp2430: Enable fan control and use Protectli logo <by Michał Żygowski>
* 75462ab838b 2024-11-28 mb/protectli/vault_adl_n: Generalize SIO config in devtree <by Michał Żygowski>
* 86f10fcb75e 2024-11-28 mainboard/protectli/vault_adl_n: Fix SIO options <by Michał Żygowski>
* dca3b4e5357 2024-11-28 src/mainboard/protectli/vault_adl_n: Enable PMC PD for all variants <by Michał Żygowski>
--squashed into 6a4c4d882ce
* 07e1c28c299 2024-11-28 mainboard/protectli/vault_adl_n/vp2430: Swap COM port I/O bases <by Michał Żygowski>
* 6e78fa01fdb 2024-11-28 configs/config.protectli_vp66xx: Enable fan control <by Michał Żygowski>
* efdb80a5440 2024-11-28 mainboard/protectli/vault_adl_p: Fix SIO options <by Michał Żygowski>
* 51ee03cfa25 2024-11-27 src/mainboard/protectli/vault_adl_n/mainboard.c: Implement fan curve options <by Michał Żygowski>
* 9a6b9b1443c 2024-11-27 src/mainboard/protectli/vault_adl_p/mainboard.c: Implement fan curve options <by Michał Żygowski>
* bad7090f67f 2024-11-27 src/mainboard/protectli/vault_adl_n: Separate ITE SIO settings <by Michał Żygowski>
* 741e412169f 2024-11-27 src/vendorcode/dasharo/include/dasharo/options.h: Add fan curve off value <by Michał Żygowski>
* 5c9eae31676 2024-12-02 3rdparty/dasharo-blobs: bump for new V1410 and V1610 descriptors <by Michał Żygowski>
* e8f5b409584 2024-12-02 mainboard/protectli/vault_jsl: Add devicetree overrides <by Michał Żygowski>
* d8b139a58b3 2024-12-02 mainboard/protectli/vault_jsl: Handle dynamic switching between NVMe and SATA <by Michał Żygowski>
* 91e363d176b 2024-12-02 configs/config.protectli_vault_jsl_v1610: Fix incorrect config <by Michał Żygowski>
--squashed into 085bf90e5db
* abd99f5bdc6 2024-11-22 mb/protectli/vault_jsl/devicetree.cb: Enable SATA in M.2 slot <by Michał Żygowski>
--XXX: contradicts ff4c53da3a2?
* feca540c91f 2024-11-22 3rdparty/dasharo-blobs: Bump for V1210 bifurcation <by Michał Żygowski>
* 627c79a46bb 2024-11-21 .github/workflows/build.yml: drop NovaCustom env <by Maciej Pijanowski>
--squashed into 8d94c845c5e
* 4631e23c7c2 2024-11-21 configs/config.dell_optiplex_9010_sff_uefi{,txt}: Bump to v0.1.1 (tag: dell_optiplex_7010_9010_v0.1.1) <by Michał Żygowski>
* c5efb148524 2024-11-21 configs/config.dell_optiplex_9010_sff_uefi_txt: Disable CMOS option backend <by Michał Żygowski>
* d4ccd5419a0 2024-11-21 mb/dell/snb_ivb_workstations/gpio.c: Configure GPIO29 as SLP_LAN# <by Michał Żygowski>
* 4af6a17b43a 2024-11-21 mb/dell/snb_ivb_workstations: Remove GPI routing settings <by Michał Żygowski>
* 0678feaf688 2024-11-12 configs/config.novacustom_n*: disable EC update <by Michał Kopeć>
--cancelled out by 2742fdda142
* 6c7f0f67197 2024-11-12 .github/workflows/build.yml: temporarily disable EC building <by Michał Kopeć>
--cancelled out by 82bf2f8f53e
* 391f86f5182 2024-11-12 .github/workflows/build.yml: build NCM MTL dGPU models too <by Michał Kopeć>
* 6efb07d3e89 2024-11-07 configs/config.novacustom_v5.0tnx: remove rc suffix <by Michał Kopeć>
* 8ad842f2dfc 2024-11-07 configs/config.novacustom_v5.0tnx: bump EDK2 to fix missing subhook module <by Michał Kopeć>
* 3abbc6ed4bc 2024-10-28 configs/config.novacustom_v5.0tnx: bump to rc8 <by Michał Kopeć>
* 070b9511f9f 2024-10-25 soc/intel/tgl: add ACPI _HIDs for DPTF power and battery <by Michał Kopeć>
* 39eef841b4b 2024-10-25 mb/clevo/mtl-h/acpi/dgpu: remove NVPCF <by Michał Kopeć>
--squashed into b6382526353
* 896ee88fb75 2024-10-25 ec/system76/ec/acpi: add DTT Power and Battery participants <by Michał Kopeć>
--replaced with e323190c978
* 89155e180f5 2024-10-18 mb/clevo/mtl-h/acpi/dgpu/gps.asl: wire up D-notifier <by Michał Kopeć>
* f1fbde68677 2024-10-18 mb/clevo/mtl-h/acpi/dgpu/gpu_ec.asl: add back D-notifier support <by Michał Kopeć>
* e37ac730179 2024-10-18 ec/system76/ec/acpi/ec_ram.asl: add d-notifier ACPI field <by Michał Kopeć>
--replaced with ecab14ce4e8
* 4166a7708d2 2024-10-16 configs/config.novacustom_v5.0tnx: fix GOP driver path <by Michał Kopeć>
* 8152f979a5f 2024-10-16 soc/intel/mtl/acpi/pcie.asl: fix RP12 IRQ mapping <by Michał Kopeć>
* ffd4007a591 2024-10-16 configs/config.novacustom_v5.0tnx: bump to rc7 <by Michał Kopeć>
* 77e4fe3cd8a 2024-10-16 configs/config.novacustom_v5.0tnx: disable DMA protection option <by Michał Kopeć>
* 108f813e0f2 2024-10-07 mb/clevo/mtl-h/ramstage.c: Add port reset message for USB ports 2 and 6 <by Michał Żygowski>
* c3f7778f39e 2024-10-14 mb/clevo/mtl-h/ramstage.c: disable S0i2.x substates <by Michał Kopeć>
* 7cd9979b351 2024-10-14 mb/clevo/mtl-h/romstage.c: add Load Line config from Clevo FW <by Michał Kopeć>
--squashed into 8aa50634892
* ebe64d4e59b 2024-10-14 mb/clevo/mtl-h/ramstage.c: move comment to start of pinmux block <by Michał Kopeć>
--squashed into 8aa50634892
* bd11029b488 2024-10-14 mb/clevo/mtl-h/inc/mainboard/variants.h: fix incorrect ifdef <by Michał Kopeć>
--squashed into ffdd9baa2bd
* 16b76b0df3b 2024-10-14 mb/clevo/mtl-h/fadt.c: remove incorrect comment <by Michał Kopeć>
--squashed into 8aa50634892
* 47a6a51dca0 2024-10-14 mb/clevo/mtl-h/dt.cb: set C-state demotion to default <by Michał Kopeć>
* 6061d17237b 2024-10-14 src/mainboard/clevo/mtl-h/Kconfig: remove S3 <by Michał Kopeć>
--squashed into 8aa50634892
* 5823f1f7246 2024-10-02 configs/config.novacustom_v5.0tnx: enable prefmem alloc above 4G <by Michał Kopeć>
* ffdd9baa2bd 2024-10-02 mb/clevo/mtl-h: detect smartamp before enabling it <by Michał Kopeć>
--squashed with bd11029b488
* 3d1fe974cc9 2024-10-02 configs/config.novacustom_v5.0tnx: disable opROM loading <by Michał Kopeć>
* d3de6614701 2024-09-27 configs/novacustom_v5.0tnx: bump edk2 for power failure string update <by Michał Kopeć>
* e3f07cd51ea 2024-09-27 configs/novacustom_v5.0tnx: bump ver to -rc6 <by Michał Kopeć>
* 18b99ff8405 2024-09-27 configs/novacustom_v5.0tnx: Enable UEFI GOP on nvidia dGPU <by Michał Kopeć>
* 9a2a4c2ca24 2024-09-23 mb/clevo/mtl-h/acpi/dgpu: fixes to make it closer to clevo FW <by Michał Kopeć>
--squashed into b6382526353
* 4ff9d35cb76 2024-09-17 mb/clevo/mtl-h/acpi/dgpu: fixes after review <by Michał Kopeć>
* c777986d1cb 2024-09-06 Fix inconsistencies with schematics <by Michał Żygowski>
--squashed into 8aa50634892 (mostly) and b6382526353 fd8afbdd02b
* 827dd3c27eb 2024-09-10 configs/config.novacustom_v5.0tnx: bump to rc5 <by Michał Kopeć>
* 1710432394e 2024-09-10 mb/clevo/mtl-h/ramstage.c: skip disabling PTT <by Michał Kopeć>
--cancelled out 40c98a4a95c
* dd0cf1f5542 2024-09-10 soc/intel/mtl/romstage/romstage.c: fix typo and add missing include for VT-d <by Michał Kopeć>
--squashed into 5e1f6ecbd39
* 5e1f6ecbd39 2024-08-28 soc/intel/meteorlake: Hook the VT-d DMA protection option <by Filip Gołaś>
--squashed with dd0cf1f5542
* c48ad905522 2024-08-23 configs/config.novacustom_v5.0tnx: bump to rc4, set static edk2 rev, disable EDK2 serial by default <by Michał Kopeć>
* 0777d9f00f9 2024-08-23 mb/clevo/mtl-h/acpi/dgpu: make dynamic boost work <by Michał Kopeć>
--squashed into b6382526353
* b1349d17bb2 2024-08-22 configs/config.novacustom_v5.0tnx: unhide HECI1 <by Michał Kopeć>
--squashed into 91d31cbcf12
* 20dd8db98af 2024-08-20 mb/clevo/var/dgpu/data.vbt: enable fixed mode <by Michał Kopeć>
--squashed into b6382526353
* baad146aad2 2024-08-20 mb/clevo/var/dgpu: fixup audio config <by Michał Kopeć>
--squashed into fd8afbdd02b
* 91c78850da5 2024-08-19 configs/config.novacustom_v5.0tnx: bump edk2 for GOP fix + bump rc ver <by Michał Kopeć>
* fd8afbdd02b 2024-08-19 clevo/mtl-h/var/dgpu: add audio configuration <by Michał Kopeć>
--squashed with baad146aad2 c777986d1cb
* 9644e31b8c5 2024-03-07 drivers/i2c/tas5825m: Use I2C instead of SMBus <by Tim Crawford>
* b6382526353 2024-08-14 mb/clevo/mtl-h: add dGPU ASL code <by Michał Kopeć>
--squashed with 20dd8db98af 39eef841b4b 9a2a4c2ca24 9a2a4c2ca24 0777d9f00f9
* 34d556d2045 2024-08-12 configs/config.novacustom_v5*tnx: disable debug, bump edk2 for dgpu, bump rc <by Michał Kopeć>
* 1627338c543 2024-08-12 mb/clevo/mtl-h/variants/dgpu: reenable dGPU <by Michał Kopeć>
--squashed into 8aa50634892
* 91d31cbcf12 2024-08-02 configs: add novacustom mtl dgpu configs <by Michał Kopeć>
--squashed with b1349d17bb2
* 062cb3523a1 2024-07-30 mb/clevo/mtl-h/variants/dgpu: uncomment unused variable <by Michał Kopeć>
--squashed into 8aa50634892
* e15cb42b480 2024-07-30 mb/clevo/mtl-h/variants/dgpu: fix TP_ATTN# pin <by Michał Kopeć>
--squashed into 8aa50634892
* 40c98a4a95c 2024-07-30 mb/clevo/mtl-h/ramstage.c: ensure PTT is disabled <by Michał Kopeć>
--cancelled out by 1710432394e
* 79f66826fe0 2024-07-30 mb/clevo/mtl-h/variants/dgpu: disable dGPU <by Michał Kopeć>
--squashed into 8aa50634892
* 2fc988b6cfa 2024-11-14 configs/config.protectli_vp32xx: Bump to v0.9.0-rc4 (tag: protectli_vault_adln_v0.9.0-rc4) <by Michał Żygowski>
* c8e450a4b07 2024-11-14 mainboard/protectli/vault_adl_n; Fix CLKREQ and CPM config on VP32xx <by Michał Żygowski>
* 6d8e0a46317 2024-11-14 configs/config.protectli_vp32xx: Bump to v0.9.0-rc3 (tag: protectli_vault_adln_v0.9.0-rc3) <by Michał Żygowski>
* fa5b8e1623a 2024-11-13 .github/workflows/deploy-template.yml: Fix VP2430 model variable (tag: protectli_vp2430_v0.9.0-rc1) <by Michał Żygowski>
--squashed into 4ea09939eeb
* e7d4d51c85c 2024-11-13 .github/workflows/deploy-template.yml: Fix exception IF for VP2430 <by Michał Żygowski>
--squashed into 4ea09939eeb
* 4ea09939eeb 2024-11-13 .github/workflows/deploy-template.yml: Add exception for VP2430 <by Michał Żygowski>
--squashed with e7d4d51c85c, fa5b8e1623a
--squashed into d904b46b78d
* 40632480dd2 2024-11-13 configs/config.protectli_vp2430: Enable missing options <by Michał Żygowski>
--could be squashed into d904b46b78d, but there are conflicts
* 10ce207b0f5 2024-11-13 .github/workflows/build.yml: Deploy VP2430 from different tag <by Michał Żygowski>
--squashed into d904b46b78d
* 503681fe5ba 2024-11-08 src/mainboard/protectli/vault_adl_n: Unify I2C and USB-PD <by Michał Żygowski>
--squashed with 8bff12cee3d
* 6a4c4d882ce 2024-11-08 mainboard/protectli/vault_adl_n: Enable W/A for missing CLKREQs <by Michał Żygowski>
--squashed into d904b46b78d dca3b4e5357
* 830d44ced0a 2024-11-08 3rdparty/dasharo-blobs: Add VP2430 blobs and FSP <by Michał Żygowski>
* d904b46b78d 2024-10-23 mb/protectli/vault_adl_n/variants: Add VP2430 variant <by Filip Lewiński>
--squashed with 6a4c4d882ce 10ce207b0f5 4ea09939eeb bdf2cb51b6e
* 054e6d2dbe2 2024-11-08 mainboard/protectli/vault_adl_n: Remove non-existing variant <by Michał Żygowski>
--squashed into d9f08f95e80
* 0a86bed4260 2024-11-07 mainboard/protectli/vault_adl_n/devicetree.cb: Enable DDC lines <by Michał Żygowski>
--squashed into d9f08f95e80
* 1ec678afdc1 2024-11-07 mb/protectli/vault_adl_n/data.vbt: Add proper VBT <by Michał Żygowski>
--squashed into d9f08f95e80
* a1d1738d856 2024-11-07 configs/config.protectli_vp32xx: Enable CBFS UUID and S/N <by Michał Żygowski>
* 26ab7d99e98 2024-11-04 configs: Fix EDK2 build with missing subhook module (dasharo/vp3200_support) <by Michał Żygowski>
* cd64aa6d70e 2024-11-04 mainboard/protectli/vault_adl_n/bootblock.c: Fix GPIO set check <by Michał Żygowski>
* b9e6ba87599 2024-10-28 mb/protectli/vault_adl_n/gpio.c: Correct GPIOs per schematics <by Michał Żygowski>
--squashed into d9f08f95e80
* b12fe1d8bd9 2024-10-28 mb/protectli/vault_adl_n/Makefile.inc: Compile die_notify in all stages <by Michał Żygowski>
--squashed into d9f08f95e80
* 66e6f317961 2024-10-28 mb/protectli/vault_adl_n/board_info.txt: Add URL <by Michał Żygowski>
--squashed into d9f08f95e80
* e74b9d11b91 2024-10-17 configs/config.protectli_vp32xx: Bump to rc2 <by Michał Żygowski>
* d2506c298fd 2024-10-16 configs/config.protectli_vp66xx: Make CI happy <by Michał Żygowski>
* 761db8e8a04 2024-10-16 mb/protectli/vault_adl_n: Provide fake CLKREQ signals <by Michał Żygowski>
--header updates were squashed into d9f08f95e80
--moved after d9f08f95e80
* e6994f1463e 2024-10-15 configs/config.protectli_vp32xx: Bump to rc1 <by Michał Żygowski>
* 89e9705cc4e 2024-10-15 .github/workflows/build.yml,build.sh: Add build automation for VP32XX series <by Michał Żygowski>
--squashed with bdf2cb51b6e
* 912cc08160e 2024-10-15 3rdparty/dasharo-blobs: Bump for VP32XX blobs <by Michał Żygowski>
* d9f08f95e80 2024-10-15 mb/protectli/vault_adl_n: Initial support for VP32XX series <by Michał Żygowski>
--broken by upstream:bfbc5cfcb2be562fc6fcf31dfcab9b648c9f81c7
worth checking that I rewrote GPIO setup correctly
--squashed with 66e6f317961 b12fe1d8bd9 054e6d2dbe2 ec14284b603 b9e6ba87599 1ec678afdc1 0a86bed4260 761db8e8a04
* bbefddd7025 2024-10-31 security/tpm: fix tis_drivers for postcar <by Sven Anderson>
* a8c2c7944b9 2024-10-30 security/tpm/tspi/log-tpm1.c: Clear whole log area on creation <by Michał Żygowski>
* 101ae8439c9 2024-10-30 util/cbmem/cbmem.c: Avoid overflwos when parsing TCG TPM logs <by Michał Żygowski>
* becd33be29b 2024-10-24 configs/config.dell_optiplex_9010_sff_uefi: Update configs (dasharo/optiplex_fixes) <by Michał Żygowski>
* b8c3422e6be 2024-10-24 southbridge/intel/common: Add support for SMM BWP option <by Michał Żygowski>
* cc826ef8def 2024-10-24 sb/intel/{common,bd82x6x}: Add support for power state after fail option <by Michał Żygowski>
* c7da8bc93b9 2024-10-24 mainboard/dell/snb_ivb_workstations: Add support for PS/2 option <by Michał Żygowski>
* 72641fac26b 2024-10-24 mainboard/dell/snb_ivb_workstations/default.fmd: Remove redundant spaces <by Michał Żygowski>
--squashed into 00d3973596a
* cbe413aaed7 2024-07-25 arch/x86/smbios.c: Strip leading spaces from CPU brand string <by Michał Żygowski>
* 19eefb53baa 2024-10-03 configs/config.hardkernel_odroid_h4: Disable verbose logging <by Michał Żygowski>
* ae2327bdb2d 2024-10-03 configs/config.hardkernel_odroid_h4: Keep S5 state after power failure <by Michał Żygowski>
* 0f1e18a7b35 2024-10-03 soc/intel/alderlake/acpi.c: Use C8 as ACPI C3 idle state for ADL-N <by Michał Żygowski>
* 34e4539d139 2024-10-03 mb/hardkernel/odroid_h4: Sync with upstream <by Michał Żygowski>
--superseded by 34c9694680b
* 7226ebce6e8 2024-10-04 .gitignore: Ignore both roms and their sha256 <by Sebastian Czapla>
* adb6e4ca144 2024-10-01 configs/config.hardkernel_odroid_h4: Make CI happy <by Michał Żygowski>
--squashed with 0eb25594639
* 52748b961f6 2024-05-27 soc/intel/mtl/acpi/gpio.asl: fix missing gpio.h include <by Michał Kopeć>
* 153ea8f4d3b 2024-10-01 3rdparty/dasharo-blobs: bump for mtl blobs <by Michał Kopeć>
* 212e924fd06 2024-09-24 src/include/spd_bin.h: introduce SPD_LEN_DDR5 <by Michał Kopeć>
* 83995f9047a 2024-09-24 soc/intel/cmn/blk/smbus/smbuslib.c: get_spd: reduce if nesting <by Michał Kopeć>
--affected by updated 188a4127b68
--squashed into 188a4127b68
* 2b68516e60c 2024-09-24 soc/intel/cmn/blk/smbus/smbuslib.c: switch_page: rename offset variable <by Michał Kopeć>
--squashed into 188a4127b68
* 526a490cacc 2024-09-11 configs/config.novacustom_v5.0tu: unify config across variants <by Michał Kopeć>
* 549f4287c21 2024-09-11 mb/clevo/mtl-h/ramstage.c: remove duplicated final newline <by Michał Kopeć>
--squashed into 8aa50634892
* 8d94c845c5e 2024-09-11 .github/workflows/build.yml: obtain novacustom-blobs <by Michał Kopeć>
--squashed with 627c79a46bb
* 802ad392737 2024-09-11 soc/intel/common/block/cse/cse_eop.c: join userfacing strings to single lines <by Michał Kopeć>
* 790f55c2ba7 2024-08-12 payloads/external/edk2: Add option to use platform lid library for GOP <by Michał Żygowski>
--squashed with 75134ab237d
* 855fdd679ec 2024-07-18 ec/system76: add delays in EC update <by Michał Kopeć>
--obsoleted by 4001267a529
* 9e0d040f2f3 2024-07-10 soc/intel/meteorlake: hook up graphics ops <by Michał Kopeć>
* 328733cff16 2024-07-09 ec/system76/ec/acpi/s76.asl: use a real ACPI PNP ID <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* 4f76d665f47 2024-07-09 src/soc/intel/meteorlake/Kconfig: disable early SOL <by Michał Kopeć>
--skipped, upstream:dfa830e53092b4b52fa548c3616873a86c3818ad removed config SOC_INTEL_METEORLAKE_SIGN_OF_LIFE
might need adjusting condition on select FSP_UGOP_EARLY_SIGN_OF_LIFE
* 2e736a20930 2024-07-05 soc/intel/mtl/romstage/fsp_params.c: disable MRC fastboot on RTC failure <by Michał Kopeć>
* 4536877fd6d 2024-06-25 soc/intel: Disable RAMTOP caching for non-ChromeOS builds <by Michał Żygowski>
* 26cda51f3f0 2024-06-12 vc/dasharo: Add API to get active cores and HT <by Michał Żygowski>
--squashed into 424e862c89e
* c03b54bf15c 2024-06-27 soc/intel/meteorlake/acpi/pcie.asl: add stubs for SRAM and HEC1 devices <by Michał Kopeć>
* 2717a1db8be 2024-03-16 soc/intel/mtl: Enable RAMTOP caching at SoC level for MTL devices <by Subrata Banik>
* 7943bbbb71d 2024-03-16 arch/x86: Add API to check if cache sets are power-of-two <by Subrata Banik>
* bd1de1702db 2024-03-16 soc/intel/cmn/ramtop: Refactor MTRR handling for RAMTOP range <by Subrata Banik>
* 2fb7a4ae07a 2024-06-05 soc/intel/mtl: Set HDA subsystem ID during FSP-M <by Tim Crawford>
* 76b923b660f 2024-06-20 soc/intel/common/cse: do not send EOP when CSE in Debug mode <by Michał Kopeć>
* 51159c157f0 2024-06-20 soc/intel/meteorlake/Kconfig: select HAVE_INTEL_ME_HAP <by Michał Kopeć>
* 391c4741250 2024-03-07 soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory <by Jeremy Soller>
* 188a4127b68 2024-05-31 soc/common/smbus: Support reading SPD5 hubs for DDR5 <by Jeremy Soller>
--upstream:60771bfdb102 caused conflict in src/soc/intel/common/block/smbus/smbuslib.c
Resolved it, but not 100% sure it's correct.
affected by upstream:e1306a39230 (smbus_read_spd() => spd_read())
--squashed with 2b68516e60c 83995f9047a ee06d88cb20
* f82311691a7 2024-06-04 soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU <by Michał Kopeć>
--skipped, in upstream as a7437ca3409eef0a906986da55cf43d6f61a1f08
* a8f5f79dcec 2024-05-24 src/soc/intel/meteorlake/Makefile.mk: use missing IoT headers from vc <by Michał Kopeć>
--squashed into ab352f8a606
* 2072032bfa9 2024-05-24 vc/intel/fsp/fsp2_0/iot/meteorlake: copy missing IoT headers to new folder <by Michał Kopeć>
* ab352f8a606 2024-05-24 soc/intel/meteorlake/Makefile.mk: include missing MemInfoHob from vendorcode <by Michał Kopeć>
--squashed with a8f5f79dcec
* 322cc5644bd 2024-05-23 lib/smbios.c: fill in BIOS characteristics depending on payload <by Michał Kopeć>
--XXX: bug in the value of BIOS_EXT2_CHARACTERISTICS_BIOS_BOOT?
* 71655743985 2024-05-23 ec/system76/ec/acpi: remove nonfunctional power button device <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* 83088cb9ad1 2024-05-23 drivers/bayhub_lv2: enable ASPM and PM L1.2 substate <by Michał Kopeć>
* 9ae5ab26c99 2024-05-22 payloads/external/edk2/Makefile: don't recurse submodules when cloning <by Michał Kopeć>
--XXX: questionable, can slow things down a bit
* 8aa50634892 2024-04-12 mb/clevo/mtl-h: add mainboard <by Michał Kopeć>
--file are moved to mb/novacustom
why adl and tgl are updated as well?
--squashed with 549f4287c21 16b76b0df3b 7cd9979b351 40e8d1a9b99 79f66826fe0 e15cb42b480 062cb3523a1 1627338c543 c777986d1cb ebe64d4e59b 6061d17237b 048ca832325
* e72799f7444 2024-05-22 payloads/external/iPXE/Makefile: bump iPXE rev for i219-lm 20 support <by Michał Kopeć>
--TODO: can be squashed
* d85f581d55c 2024-05-22 3rdparty/fsp: bump for MTL IoT FSP <by Michał Kopeć>
* 19ab8aef9ec 2024-05-21 soc/intel/mtl: enable common VTD block <by Michał Kopeć>
* 9ff63111cae 2024-05-21 soc/intel/mtl: hook up public ucode <by Michał Kopeć>
--skipped, upstream has cfcb3620acd4187f143fc3b129dd21b2aa34f1d8
I think upstream version should work for us
* 8f685861330 2024-05-15 soc/intel/meteorlake/Kconfig: allow FSP-M SOL on non-Chrome <by Michał Kopeć>
--skipped, dfa830e53092b4b52fa548c3616873a86c3818ad removed config SOC_INTEL_METEORLAKE_SIGN_OF_LIFE
I think upstream version should work for us
* 61180f50ac4 2024-05-15 soc/intel/meteorlake/fsp_params.c: wire up connection manager Kconfig option <by Michał Kopeć>
--XXX: because upstream:a0975050fa01 this now only contains (accidental?) change to FspEventHandler
* 0007c46d0cf 2024-05-15 soc/intel/mtl/chip.c: Add two missing ACPI device names <by Michał Kopeć>
--squashed into fca8a0f784b
* fca8a0f784b 2024-05-06 src/soc/intel/meteorlake/chip.c: add missing DPTF device name <by Michał Kopeć>
--squashed with 0007c46d0cf
* 84a7af85cdf 2024-05-06 meteorlake/romstage/fsp_params.c: wire up DMA protection <by Michał Kopeć>
* c6c17ef214f 2024-04-28 soc/intel/mtl: hook up pch_hda_audio_link_hda_enable <by Michał Kopeć>
* 3c1c7741caf 2024-04-28 soc/intel/common/block/graphics: hook up graphics ops for MTL <by Michał Kopeć>
* ffc0c5d12fe 2024-04-28 include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU ID <by Michał Kopeć>
* 7dc094111e6 2024-09-24 configs/config.hardkernel_odroid_h4: Bump to rc2 <by Michał Żygowski>
* 0eb25594639 2024-09-24 configs/config.hardkernel_odroid_h4: Add Intel blobs <by Michał Żygowski>
--squashed with adb6e4ca144
* 602dca3942e 2024-09-24 3rdparty/dasharo-blobs: bump for ODROID H4 blobs <by Michał Żygowski>
* bd294ab1d22 2024-09-13 mb/qemu-q35/*.fmd: add BOOTSPLASH region (dasharo/qemu-boot-logo, qemu-boot-logo) <by Sergii Dmytruk>
* af7c369ee99 2024-09-13 mb/qemu-q35/board.fmd: add <by Sergii Dmytruk>
* 313ef1fb56b 2024-09-10 configs/config.protectli_vp2410: use Dasharo/edk2-platforms (dasharo/fix-edk2-commit-in-configs, fix-edk2-commit-in-configs) <by Sergii Dmytruk>
* 9a7523fb704 2024-09-10 payloads/edk2/Makefile: detect invalid commit hash on checkout <by Sergii Dmytruk>
* fa204693b8c 2024-09-10 configs/*: update Dasharo EDK2 revision to fix build <by Sergii Dmytruk>
--squashed into 05adc352a59
* 691bec1b71b 2024-06-15 .github/workflows/code-checks.yml: run util/lint (dasharo/add-ci-code-checks, add-ci-code-checks) <by Sergii Dmytruk>
* 82f2d8134bf 2024-06-15 mb/*: remove trailing newlines <by Sergii Dmytruk>
* fdb99c8c7bb 2024-06-15 .github/workflows/code-checks.yml: verify defconfigs are up-to-date <by Sergii Dmytruk>
* 46a38fef2cd 2024-06-14 configs: run savedefconfig on Dasharo EDK boards <by Sergii Dmytruk>
* d5edb70ef7b 2024-09-05 .github/workflows/build.yml: Build ODROID H4 (tag: hardkernel_odroid_h4_v0.9.0-rc1) <by Michał Żygowski>
* c94003a3355 2024-08-18 soc/intel/{common,alderlake}: Add missing ADL-N SKUs <by Michał Żygowski>
--skipped, it's upstream:d6d83c19128f2605a604f23c3989d84784a3e7e0
* 0efbb882a3d 2024-08-08 mainboard/hardkernel: Add ODROID H4 initial support <by Michał Żygowski>
--superseded by 34c9694680b
* 56f850cfa2b 2024-08-08 superio/ite/it8613e/it8613e.h: Add definitions for GPIO init <by Michał Żygowski>
--upstream:bfbc5cfcb2be562fc6fcf31dfcab9b648c9f81c7 and maybe other rebase changes obsolete this
* 8f3798d4c93 2024-08-08 soc/intel/alderlake/fsp_params.c: Omit W/A on ADL-N <by Michał Żygowski>
--skipped, upstream:491afc3cc778 does the same
1dc8f0272bd222125d2d26cfa2b311f3d134f6ca removed !CONFIG(SOC_INTEL_RAPTORLAKE)
* 9bfb510dc46 2024-08-29 configs/config.dell_optiplex_9010_sff_*: bump up to v0.1.0 <by Filip Lewiński>
* dcc7cf72f10 2024-08-01 .github/workflows/build.yml: add legacy OptiPlex <by Filip Lewiński>
* c9e9499c701 2024-08-01 .github/workflows/build.yml: build_optiplex - improve readability <by Filip Lewiński>
--squashed into 235cbdc395a
* 5e6b81dfe94 2024-08-01 configs/config.dell_optiplex_9010_sff_uefi*: add iPXE script <by Filip Lewiński>
* 235cbdc395a 2024-07-31 .github/workflows/build.yml: add OptiPlex to build CI <by Filip Lewiński>
--squashed with c9e9499c701
* 15a150d7b0c 2024-07-30 configs/config.dell_optiplex_9010_sff_uefi*: remove redundant flags <by Filip Lewiński>
* eac21b6a485 2024-07-30 src/mainboard/dell/snb_ivb_workstations/default.fmd: improve readability <by Filip Lewiński>
--squashed into 00d3973596a
* 14e962e7a46 2024-07-30 build.sh: fix OptiPlex description <by Filip Lewiński>
--squashed into b1fc5681686
* 00d3973596a 2024-07-29 src/mainboard/dell/snb_ivb_workstations/default.fmd: add <by Filip Lewiński>
--squashed with eac21b6a485 72641fac26b
* 9ed5a717af8 2024-07-29 configs/config.dell_optiplex_9010_sff_uefi_txt: add <by Filip Lewiński>
* 2fcbd18c847 2024-07-29 src/security/intel/txt/romstage.c: include pmutil.h to resolve missing definitions <by Filip Lewiński>
--squashed into cb921bda9e0
* 145a6f441e3 2024-07-29 src/security/intel/txt/common.c: use #IF on TPM2-only code <by Filip Lewiński>
--squashed into 982f94aa551
* b1fc5681686 2024-07-29 build.sh: add Dell OptiPlex 7010/9010 <by Filip Lewiński>
--squashed with 14e962e7a46
* 4706227e009 2024-07-30 Update util/txesbmantool/txesbmantool.c (limit-tpm2-hashes) <by Michał Żygowski>
--squashed into f2e7eb53621
* c8ba2c2a8fc 2024-07-25 Update util/txesbmantool/txesbmantool.c <by Michał Żygowski>
--squashed into 8eb2ac841c3
* cd536e47e90 2024-07-25 util/txesbmantool/txesbmantool.c: Fix coding style <by Michał Żygowski>
--squashed into 8605c1af187
* f2e7eb53621 2024-07-25 util/txesbmantool: Print key hashes when displaying manifests <by Michał Żygowski>
--squashed with 4706227e009
--squashed into 8605c1af187
* 3fa1424d7eb 2024-07-25 util/txesbmantool/.gitignore: Ignore the resulting executable <by Michał Żygowski>
--squashed into 8605c1af187
* 477680c1009 2024-07-25 util/txesbmantool: Fix missing target directory during build <by Michał Żygowski>
--squashed into 8605c1af187
* 8eb2ac841c3 2024-07-24 util/txesbmantool/txesbmantool.c: Refactor for single manifest structure <by Michał Żygowski>
--squashed with c8ba2c2a8fc
* d1021530727 2024-07-24 util/txesbmantool/README.md: Add missign error output <by Michał Żygowski>
--squashed into 8605c1af187
* 6e5303b7324 2024-06-13 util/txesbmantool/txesbmantool.c: Refactor inefficient parts <by Michał Żygowski>
--squashed into 8605c1af187
* dfe0b98463c 2024-06-13 Apply suggestions from code review <by Michał Żygowski>
--squashed into 8605c1af187
* e5988390a6e 2024-04-17 soc/intel/baytrail: Generate TXE SB manifests after build <by Michał Żygowski>
* 8605c1af187 2024-04-17 util/txesbmantool: Add utility to generate TXE SB manifests <by Michał Żygowski>
--squashed with dfe0b98463c, 6e5303b7324, d1021530727, 477680c1009, 3fa1424d7eb, cd536e47e90 f2e7eb53621
* 05adc352a59 2024-07-26 configs/*: Update edk2 revision to include new help message <by Filip Gołaś>
--squashed with fa204693b8c
* 540dd4f6d03 2023-10-24 mb/clevo/adl-p: Add HDA verbs from vendor BIOS <by Michał Żygowski>
--squashed into 1c9034a509c
* ff68728477a 2024-07-05 .github/workflows/build.yml: add deploy jobs (dasharo/deploy-worflow) <by Pawel Langowski>
--squashed with 56b50c1e3e2
* ff4c53da3a2 2024-07-11 mainboard/protectli/vault_jsl/devicetree.cb: Disable SATA <by Michał Żygowski>
--squash with f1a0f7e8c0d but move comment into the code??
--XXX: contradicts abd99f5bdc6?
* abb58d8f4c1 2024-07-01 security/vboot/Makefile.mk: silence warnings when signing binary <by Michał Kopeć>
--TODO: the workaround can be dropped if we bump vboot in our fork
* 1cbcd54e79b 2024-06-20 configs: Update edk2 revision to reworked CPU throttling (dasharo/throttling_rework_24.02) <by Michał Żygowski>
* 6e0f89e8298 2024-06-20 soc/intel/common/block/cpu/cpulib.c: Update TCC offset mask <by Michał Żygowski>
* 84ec3daa660 2024-06-20 src/mainboard/protectli: Override default throttling value for boards <by Michał Żygowski>
* 5077ceba6a6 2024-06-20 intel platforms: Integrate overriding TCC offset <by Michał Żygowski>
* c76d06dfade 2024-06-20 payloads/external/edk2: Add CPU throttling options <by Michał Żygowski>
* 89b48406036 2024-06-20 vc/dasharo: Add CPU throttling options API <by Michał Żygowski>
* 26c5df90375 2024-06-18 .github/workflows/build.yml: add QEMU Q35 to platforms built by CI (tag: qemu_q35_v0.2.0-rc1, tag: qemu_q35_v0.2.0, dasharo/dasharo-payload-pkg) <by Krystian Hebel>
* 0d00fc3cc85 2024-06-04 build.sh: add function for building QEMU Q35 image <by Krystian Hebel>
* b3afb4202be 2024-06-20 configs/config.emulation_qemu_x86_q35_uefi_all_menus: add file <by Krystian Hebel>
* dcdde2e90bd 2024-05-24 configs/config.emulation_qemu_x86_q35_uefi: add config for platform <by Krystian Hebel>
* f19fd2a516f 2024-05-25 payloads/edk2: pass information about use of edk2-platforms <by Krystian Hebel>
* a4239867ea0 2024-05-25 acpi/acpi.c: fix XSDT handling on QEMU <by Krystian Hebel>
--skipped, because upstream:4b43dac16b46, although I remember there were some issues with upsteam fix
* a3197c82d89 2024-05-24 mb/qemu-{i440fx,q35}: reduce default ROM size to 8 MiB <by Krystian Hebel>
* 874696a8df0 2024-05-20 mb/qemu-q35/smihandler.c: add support for SMIs on QEMU <by Krystian Hebel>
* 2cd5cd25aa3 2024-05-15 mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash <by Krystian Hebel>
* 8c0d44cd3c8 2024-04-25 configs/: update EDK2 revision after rebasing (dasharo-payload-pkg) <by Sergii Dmytruk>
* 713cff070ed 2024-04-24 payloads/edk2: build DasharoPayloadPkg <by Sergii Dmytruk>
* 5b6805c880e 2024-06-19 configs: Bump edk2 to fix FUM variable handling <by Michał Żygowski>
--squashed into bc00971eaef
* d3b853142a2 2024-06-19 drivers/pc80/tpm/tis.c: Fix probing for the TPM family <by Michał Żygowski>
* bc00971eaef 2024-06-19 configs: Bump edk2 revision to let all boards build with newest changes <by Michał Żygowski>
--squashed with 5b6805c880e
* 31a63aa5760 2024-06-13 configs/config.protectli_vp66xx: bump to rc5 <by Michał Żygowski>
* 7502e10b884 2024-06-12 configs/config.protectli_vp66xx: Update config for CPU downcoring and HT <by Michał Żygowski>
* 78e2643a1dc 2024-06-12 mainboard/protectli/vault_adl_p/devicetree.cb: Disable AER on WIFI slot <by Michał Żygowski>
* 0bad6cd7a4a 2024-06-12 payloads/external/edk2: Add Kconfig options for CPU downcoring and HT <by Michał Żygowski>
* 95f8459de5b 2024-06-12 soc/intel/alderlake: Integrate downcoring and HT option <by Michał Żygowski>
* 424e862c89e 2024-06-12 vc/dasharo: Add API to get active cores and HT <by Michał Żygowski>
--squashed with 26cda51f3f0
* 7537c39378b 2024-06-19 intelblocks/me_18.h: Add HAP location for MTL U/H <by Michał Żygowski>
* 7babb8f311c 2024-06-18 .github/workflows/build.yml,build.sh: Enable automated builds for V1211 <by Michał Żygowski>
* dadd883ed5f 2024-06-18 mainboard/protectli/vault_jsl: Add V1211 support (dasharo/v1211_support_rebased) <by Michał Żygowski>
* 93a1ad17ee3 2024-06-11 mb/protectli/vault_jsl: disable HWP <by Maciej Pijanowski>
* add477bf787 2024-06-14 3rdparty/intel-microcode: Bump to microcode-20240531 <by Michał Żygowski>
* 99ce11a6660 2024-05-08 mainboard/protectli/vault_adl_p: Poll for IOM_READY before FSP-S <by Michał Żygowski>
--skipped, seems to be part of upstream:256e98f60471ed21067af4f91e986dccb619145e
* 24906e70c23 2024-05-08 src/soc/intel/alderlake/Kconfig: Deprecate ADL FSP <by Michał Żygowski>
--needs verification
upstream changed sorting, conditions and formatting
* bcda1de2a24 2024-05-08 3rdparty/fsp: Update submodule <by Michał Żygowski>
* 26e4861aa68 2024-05-08 3rdparty/dasharo-blobs: Update VP66xx blobs <by Michał Żygowski>
* 3467810c971 2024-05-08 cpu/x86/pae/pgtbl.c: extract reusable code from memset_pae() (pae_map) <by Krystian Hebel>
* 595c4b42242 2024-05-13 security/memory_clear: fix wrong size of reserved memory range <by Krystian Hebel>
* cdb24f9abda 2024-05-08 cpu/x86/pae/pgtbl.c: remove dead paging_identity_map_addr() <by Krystian Hebel>
* a1704b0e71d 2024-05-07 cpu/x86/pae/pgtbl.c: remove dead map_2M_page() <by Krystian Hebel>
* f6e1bbb9b3c 2024-05-28 mainboard/protectli/vault_ehl: Disable HWP <by Michał Żygowski>
* 9d0ab93d850 2024-05-24 configs/config.protectli_vp2420: Disable HECI at pre-boot <by Michał Żygowski>
* a76d969c071 2024-05-29 configs/config.protectli_vp46xx_txt_seabios: Udpate TXT config (dasharo/vp4670_txt) <by Michał Żygowski>
* 8383a1e24fa 2024-05-20 3rdparty/intel-microcode: Bump to microcode-20240514 <by Michał Żygowski>
--skipped
* 7fa65d2fa24 2024-05-19 src/drivers/intel/ptt/Makefile.mk: Compile PTT in bootblock <by Michał Żygowski>
* b151ce8f64f 2024-05-19 src/soc/intel/common/block/cse/cse.c: Handle default ME state properly <by Michał Żygowski>
* 9a5e8dbee3e 2024-05-19 drivers/tpm: Disable TPM driver if probe fails <by Michał Żygowski>
* 7ddf707f6d3 2024-04-24 drivers/crb,pc80/tpm: Add crb and pc80 prefixes to chip configs <by Michał Żygowski>
* de18e90bb03 2024-05-13 src/mainboard/protectli/vault_jsl: Add new SPD for V1210 <by Michał Żygowski>
--squashed into f1a0f7e8c0d
* 6cd77aa95a7 2024-05-13 src/mainboard/clevo/adl-p/Kconfig: Add missing TPM PIRQ for NV41 <by Michał Żygowski>
--squashed into 1c9034a509c
* ff034e6b59f 2024-05-09 configs: bump edk2 for WDT visibility <by Michał Kopeć>
* 207989f0d21 2024-05-08 payloads/external/edk2/Makefile: fix passing OC WDT PCDs <by Michał Kopeć>
* 2c62a70f1cd 2024-05-08 mb/protectli/vault_cml/Kconfig: restore previous order of options <by Michał Kopeć>
* 58bb60168f8 2024-05-08 oc_wdt/Kconfig: set default timeout if WDAT is enabled <by Michał Kopeć>
* ba085cb018d 2024-05-08 configs/config.protectli_*: enable ACPI WDAT for ADL, CML, EHL <by Michał Kopeć>
* b01bf35db95 2024-05-08 mb/protectli/vault_cml/Kconfig: disable WDAT in board Kconfig <by Michał Kopeć>
--cancelled out bc31f11e37f
* 36b009dd9bd 2024-05-08 block/oc_wdt/acpi.c: add missing include <by Michał Kopeć>
--squashed into 9cc779c8bce
* abcb5f5dbaa 2024-04-15 oc_wdt/acpi.c: switch back to 32bit accesses <by Michał Kopeć>
--squashed into 9cc779c8bce
* 278cc512722 2024-03-15 oc_wdt: ignore WDT_ENABLE when enabling <by Michał Kopeć>
* 9f5f4da674d 2024-03-15 oc_wdt: add prompt for WDAT <by Michał Kopeć>
--squashed into 9cc779c8bce
* ccab13298e6 2024-05-08 edk2: add knob to control watchdog default state <by Michał Kopeć>
* efde5000f72 2024-03-15 src/vendorcode/dasharo/options.c: fix incorrect WDT default state <by Michał Kopeć>
* 2b124d86842 2024-03-15 soc/intel/cmn/blk/oc_wdt: adjust access sizes <by Michał Kopeć>
--squashed into 9cc779c8bce
* bc31f11e37f 2024-03-14 vault_cml: enable OC WDT with WDAT <by Michał Kopeć>
--cancelled out by b01bf35db95
* 4c756d6ea30 2024-03-14 oc_wdt: don't reload in SMI and don't force WDT start if WDAT is used <by Michał Kopeć>
* 4eee079fd35 2024-03-14 soc/intel/cmn/blk/oc_wdt: store bootstatus in scratch register bits <by Michał Kopeć>
--squashed into 9cc779c8bce
* 9cc779c8bce 2024-03-14 soc/intel/cmn/blk/oc_wdt: implement ACPI WDAT <by Michał Kopeć>
--upstream:531c45e075c3 adds acpi_soc_fill_wdat() unconditionally if CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI is set for TCO watchdog
had to add #ifdef there so it's not defined when OC watchdog is to be exposed via WDAT
--squashed with 4eee079fd35 2b124d86842 9f5f4da674d abcb5f5dbaa 36b009dd9bd
* 4f2645ba30e 2024-03-14 src/acpi/acpi.c: fix incorrect weak function signature <by Michał Kopeć>
--squashed into c655cc88d06
* c655cc88d06 2024-03-14 soc/intel/cmn/blk: move WDAT acpigen for TCO to smbus block <by Michał Kopeć>
--squashed with 4f2645ba30e
* ea5577cb361 2024-05-08 .github/workflows/build.yml: fix EC artifact passing <by Michał Kopeć>
--squashed into af431315126
* 3228aa99905 2024-05-08 .github/workflows/build.yml: build on PRs to dasharo-24.02.1 <by Michał Kopeć>
--dropped
* af431315126 2024-05-08 .github/workflows/build.yml: build EC for novacustom <by Michał Kopeć>
--squashed with ea5577cb361
* 4f6fd6f278a 2024-04-15 ec/system76/ec: trigger vboot error on update failure <by Michał Kopeć>
--obsoleted by 4001267a529
* 2261b493a5c 2024-04-12 styling fixes <by Michał Kopeć>
--obsoleted by 4001267a529
* 19ff6d0ee02 2024-04-12 ec/system76/ec: cbfs_load ec update into memory <by Michał Kopeć>
--obsoleted by 4001267a529
* 7013e921360 2024-04-11 ec/system76/ec: compress EC update <by Michał Kopeć>
--obsoleted by 4001267a529
* c8768052917 2024-04-11 ec/system76/ec/system76_ec.c: free() after malloc() <by Michał Kopeć>
--obsoleted by 4001267a529
* 9bfcfc080fa 2024-04-11 ec/system76/ec/system76_ec.c: make code style consistent <by Michał Kopeć>
--obsoleted by 4001267a529
* 7648e165301 2024-04-11 Apply clang format-patch <by Michał Kopeć>
--obsoleted by 4001267a529
* 287c6b5f4fb 2024-04-11 ec/system76/ec/system76_ec.c: fix return value signedness <by Michał Kopeć>
--obsoleted by 4001267a529
* 7d9f7e106e1 2024-04-11 3rdparty/ec: remove submodule <by Michał Kopeć>
--obsoleted by 4001267a529
* 60b45dd6eb7 2024-04-11 ec: store AC adapter check fail as vboot recovery reason <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* 80ecccf61cf 2024-01-22 System76 EC firmware update in ramstage <by Michał Kopeć>
--replaced with 4001267a529
* 8a2c24cc5a5 2024-04-15 configs/config.protectli_vp66xx: Bump to v0.9.0-rc3 <by Michał Żygowski>
* 8ed0981dc4e 2024-04-15 configs/config.protectli_vp66xx: Enable PCIe ASPM L1 and CPM <by Michał Żygowski>
* ed288293cd0 2024-04-15 mb/protectli/vault_adl_p: Change FSP type to IoT for pwr/clk gating bug <by Michał Żygowski>
* f8d51ef980f 2024-04-15 mb/protectli/vault_adl_p/devicetree.cb: Assign CLKSRCs and enable ASPM <by Michał Żygowski>
--seems to be part of upstream:256e98f60471ed21067af4f91e986dccb619145e
Difference with upstream for `device ref pcie_rp10 on`:
- this commit
`.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,`
- upstream
`.flags = PCIE_RP_LTR | PCIE_RP_CLK_REQ_UNUSED,`
* 0e722284bd3 2024-04-15 mb/protectli/vault_adl_p: Enable CPM on RP5 and RP6 <by Michał Żygowski>
* 3656ca52969 2024-04-09 src/mainboard/protectli/vault_adl_p: Enable AER and 256B Max Payload <by Michał Żygowski>
--skipped, seems to be part of upstream:256e98f60471ed21067af4f91e986dccb619145e
* 9e0c367e50a 2024-04-08 soc/intel/apollolake: Select NO_MSR_SPCL_CHIPSET_USAGE <by Michał Żygowski>
* 961d3746fc3 2024-04-08 soc/intel/apollolake: Select TCO and SMBUS blocks <by Michał Żygowski>
* 8cfdedc94fe 2024-04-08 intelblocks/smm: Add Kconfig option to skip MSR_SPCL_CHIPSET_USAGE write <by Michał Żygowski>
* 0f47e391d4a 2024-04-08 src/mainboard/protectli/vault_adl_p/devicetree.cb: Add TCC offset <by Michał Żygowski>
* b02dc09e2a0 2024-04-03 configs/config.protectli_vp66xx: Bump to rc2 <by Michał Żygowski>
* d3ccc013b03 2024-04-03 configs/config.protectli_vp66xx: Use HAP to disable ME <by Michał Żygowski>
* 60c7f4c4c8c 2024-04-03 configs/config.protectli_vp66xx: Build full image <by Michał Żygowski>
* 22bdd25c198 2024-04-16 src/soc/intel/baytrail: Fix ucode and manifests offsets <by Michał Żygowski>
--squashed into 8a2a1bc8955
* caa3761b644 2024-04-16 soc/intel/baytrail/Kconfig: Enable early SPI writes for EFI variable store <by Michał Żygowski>
* ae838aa2a4c 2024-04-15 mb/clevo/tgl-u: update VBT for FSP A.0.7E.70 <by Michał Kopeć>
* d18b4e25b46 2024-04-10 src/soc/intel/baytrail: Add missing southcluster init <by Michał Żygowski>
* 10891b63528 2024-04-10 src/soc/intel/baytrail/acpi/lpc.asl: include COM1 device when enabled built in UART <by Michał Żygowski>
* db8482a296a 2024-04-10 src/mainboard/intel/minnowmax/acpi_tables.c: set USB and DPTF NVS <by Michał Żygowski>
--squashed into 1d504c03f96
* 09451dd528a 2024-04-10 src/soc/intel/baytrail/lpss.c: Configure I2C pins <by Michał Żygowski>
* 58c6301cf8f 2024-04-10 src/soc/intel/fsp_baytrail/southcluster.c: add missing disable masks for devices <by Michał Żygowski>
* a2929adc446 2024-04-10 src/mainboard/intel/minnowmax/acpi_tables.c: set PM profile to mobile <by Michał Żygowski>
--squashed into 1d504c03f96
* 7cae9799712 2024-04-10 soc/intel/baytrail/southcluster.c: Finalize SMM <by Michał Żygowski>
* fbca373e1fe 2024-04-12 src/soc/intel/baytrail/cpu.c: Fill SMBIOS type 4 information <by Michał Żygowski>
* b359752ad45 2024-04-12 src/soc/intel/baytrail: Separate MRC debug prints option in Kconfig <by Michał Żygowski>
* 05f8f344964 2024-04-11 payloads/external/edk2: Ensure edk2 path exists before copying artifacts <by Michał Żygowski>
--squashed into 119e8053285
* 55718fce6a7 2024-04-09 configs/config.intel_minnowmax: Finalize config <by Michał Żygowski>
--squashed into 1d504c03f96
* abf26066c0e 2024-04-09 payloads/external/edk2/Makefile: Enable serial terminal if requested <by Michał Żygowski>
* a55284e3d22 2024-04-09 payloads/external/iPXE/Makefile: Build iPXE for EFI target if requested <by Michał Żygowski>
* 438df4e449f 2024-04-09 src/soc/intel/baytrail/Kconfig: Add missing UDK binding <by Michał Żygowski>
--can be squashed with something?
* 2421f9025e8 2024-04-09 src/vendorcode/dasharo/options.c: Use proper Kconfig option for CSE <by Michał Żygowski>
--squashed into 8040bd2b891
* ded22d037ea 2024-04-09 payloads/external/edk2/Makefile: Revert custom changes <by Michał Żygowski>
--squashed into 119e8053285
* 1d504c03f96 2024-04-09 src/mainboard/intel/minnowmax: Add board support with Bay Trail MRC <by Michał Żygowski>
--squashed with 55718fce6a7 a2929adc446 db8482a296a
* 8a2a1bc8955 2024-04-09 soc/intel/baytrail: Add TXE Secure Boot options and placeholder for manifests <by Michał Żygowski>
--squashed with 22bdd25c198
* 7dd012156d3 2024-04-09 src/soc/intel/baytrail/romstage/romstage.c: Print TXE status <by Michał Żygowski>
* 90930b6f75f 2024-04-09 soc/intel/baytrail/include/soc/gpio.h: Add function to configure single GPIO <by Michał Żygowski>
* 80a5fd1b866 2024-04-09 soc/intel/baytrail/include/soc/gpio.h: Add macros to for legacy GPIO access <by Michał Żygowski>
* 7eb42e42a29 2024-04-09 cpu/intel/microcode: Allow loading ucode from predefined location <by Michał Żygowski>
* 27d5001e65e 2024-04-09 src/soc/intel/baytrail/bootblock/bootblock.c: Add proper UART init via PMC <by Michał Żygowski>
* c3f79301619 2024-04-04 drivers/smmstore/ramstage.c: retry smmstore init up 5 times <by Michał Kopeć>
--dropped because of upstream:d57d5e3b3737607e4351ba460d0248a195279f2d
is this OK for us, should everything still work fine? Seems to work.
* 2d7accd765d 2024-04-04 .github/workflows/build.yml: bump GH actions to latest versions <by Michał Kopeć>
* 406e5accebb 2024-04-04 msi_id: place in .init section of bootblock <by Michał Kopeć>
* f1d60a3c061 2024-04-03 superio/ite/it8659e/superio.c: fix chip name definition <by Michał Kopeć>
* b225fd17d48 2024-04-03 mb/protectli/vault_jsl: update for dt changes <by Michał Kopeć>
--squashed into f1a0f7e8c0d
* 5b483c5e43c 2024-04-03 .github/workflows/build.yml: build protectli outside of container <by Michał Kopeć>
--squashed into c5d2d952941
* ee8b505ae48 2024-04-03 build.sh: build all boards in the same sdk rev <by Michał Kopeć>
* 173df7ae4f7 2024-04-03 .github/workflows/build.yml: remove obesolete variable matrix.build <by Michał Kopeć>
* c5d2d952941 2024-04-03 .github/workflows/build.yml: use generic env for Protectli <by Michał Kopeć>
--squashed with 5b483c5e43c
--squashed into d9e33a06783
* 4fe4fbf915c 2024-04-03 drivers/gfx/nvidia/optimus: fix chip name syntax <by Michał Kopeć>
* d4c28312d77 2024-04-03 mb/clevo/tgl-u: update dt syntax for usb ports <by Michał Kopeć>
--squashed into 1c9034a509c
* 9f36b425a20 2024-04-03 payloads/edk2/Makefile: skip setting ReBAR pcd for Dasharo <by Michał Kopeć>
* a1170e32b73 2024-04-03 mb/novacustom: appease checkpatch <by Michał Kopeć>
--squashed into 1c9034a509c
* 94a75bff90b 2024-04-03 3rdparty/dasharo-blobs: add submodule <by Michał Kopeć>
* b5560ff26ba 2024-04-03 vc/dasharo/options.c: fix renamed symbol EDK2_HAVE_INTEL_ME_HAP <by Michał Kopeć>
* 51740cb5bf8 2024-04-03 edk2: fix renamed symbol EDK2_SECURE_BOOT <by Michał Kopeć>
* bad721d9d02 2024-04-03 mb/pcengines/apu2/var/apu6/devicetree.cb: use device references <by Michał Kopeć>
* c2e08b04822 2024-04-03 configs: update edk2 to fix compilation under newer sdk <by Michał Kopeć>
* 055dfffad88 2024-04-03 .github/workflows/build.yml: force workflow run on this branch <by Michał Kopeć>
* 97775d44ad8 2024-04-03 .github/workflows/build.yml: bump sdk rev <by Michał Kopeć>
* 236da101d44 2024-04-03 mb/protectli/vault_cml/Kconfig: fix renamed Kconfig symbol <by Michał Kopeć>
--squashed into 9646f0e0f65
* 9646f0e0f65 2024-02-15 mainboard/protectli/vault_cml: Enable VBOOT_ENABLE_CBFS_FALLBACK <by Michał Żygowski>
--squashed with 236da101d44
--changed title to "mb/protectli/vault_cml: Enable VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE"
* 083adcc24ed 2023-10-27 mb/protectli/vault_cml/vboot-rwa.fmd: update layout for more space <by Michał Kopeć>
* 9ad702d84b1 2023-10-26 mb/protectli/vault_cml: remove deprecated lapic declaration <by Michał Kopeć>
--squashed into 1dbc6aabe7d
* 1dbc6aabe7d 2023-10-26 mb/protectli/vault_cml: begin migration to 4.21 <by Michał Kopeć>
--TODO: Why `- select HAVE_INTEL_PTT`?
correctly edited src/mainboard/protectli/vault_cml/devicetree.cb ?
--squashed with 9ad702d84b1
--changed title to "mb/protectli/vault_cml: add Dasharo modifications"
* d49bddb0b77 2022-11-01 security/tpm: support compiling in multiple TPM drivers <by Sergii Dmytruk>
* 535d6e9de82 2024-04-03 Resolve compilation issues after rebase <by Michał Kopeć>
--squashed into 766300c3d7b, 94ad70fb9dc, 6ede7817339
* 8ce250a3efd 2024-04-03 soc/intel/{tgl,adl}: add ME disable options <by Michał Kopeć>
* a7980a03377 2024-04-03 vc/dasharo: fix renamed Kconfig symbol <by Michał Kopeć>
--TODO: squash somewhere?
* b75374fb9a0 2024-04-03 cpu/amd/pi/Kconfig: disable preram CBFS cache <by Michał Kopeć>
* 982f94aa551 2024-04-03 Make the dual TPM code compile <by Michał Kopeć>
--squashed with 145a6f441e3
--squashed into d58587c50f8 857127eec4e
* e0f7b710686 2024-03-30 drivers/tpm: Make it compile again <by Patrick Rudolph>
* 1e7d5213ffa 2022-11-02 security/tpm: replace CONFIG(TPMx) checks with runtime check <by Sergii Dmytruk>
* bc9ed4529b5 2022-10-31 security/tpm: resolve conflicts in TSS implementations <by Sergii Dmytruk>
* 1898e388dca 2022-10-31 security/tpm: make tis_probe() return tpm_family <by Sergii Dmytruk>
* 11bb74fb4a1 2024-04-03 Revert "sb/amd/pi/hudson: select HAVE_CONFIGURABLE_APMC_SMI_PORT" <by Michał Kopeć>
* 0e2a958c886 2024-01-31 device/pciexp_device.c: Fix setting Max Payload Size <by Michał Żygowski>
* a89d0e6783c 2024-04-03 /commonlib/bsd/cbmem_id.h: fix build after rebase <by Michał Kopeć>
--squashed into d3deb836eff
* e1306a39230 2024-04-03 src/security/tpm/tss/tcg-2.0/tss.c: fix compilation of nv_read_public after rebase <by Michał Kopeć>
--squashed into d58587c50f8
* 119e8053285 2024-04-03 edk2: add Dasharo options to build <by Michał Kopeć>
--squashed with ded22d037ea 05f8f344964
* 21e6313ae8d 2024-04-03 payloads/external/Makefile.mk: pass Dasharo options to edk2 <by Michał Kopeć>
--should be split?
* e47467f845f 2024-04-03 payloads/Kconfig: source Dasharo specific options from a separate Kconfig file <by Michał Kopeć>
* 6e90a45c4b8 2018-12-28 payloads/iPXE: option for reproducible building <by Signed-off-by: Krystian Hebel>
* c37a562f878 2024-04-02 configs: fix renamed PXE config options <by Michał Kopeć>
* f4828a610e6 2024-04-02 mb: use VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE instead of VBOOT_CLEAR_RECOVERY_EACH_BOOT <by Michał Kopeć>
--TODO: squash?
* e66700d58ad 2024-04-02 mb/apu2/variants/apu{3,4}/devicetree.cb: add TPM device node <by Sergii Dmytruk>
* b7dca39237d 2024-03-28 build.sh: Ensure the apus are built from UEFI configs <by Michał Żygowski>
* ea6b1410249 2024-03-27 .github/workflows/build.yml: use uefi defconfigs for pcengines <by Michał Kopeć>
* 50e4640afa5 2024-03-27 configs/config.pcengines_uefi_apu*: add defconfigs <by Michał Kopeć>
* 976486ae276 2024-03-20 mb/msi/ms7d25,ms7e06/msi_id.S: Fix major version in MSI signature on DDR4 boards <by Michał Żygowski>
--squashed into 57d63a016fb 4fad064a8c5
* 30e69de844a 2024-03-20 mb/msi/ms7d25,ms7e06/msi_id.S: Fix FlashBIOS on DDR4 v0.9.x builds <by Michał Żygowski>
--squashed into 57d63a016fb 4fad064a8c5
* f7c2cc544b0 2024-03-15 Makefile.inc: Reword the description of sort-files <by Michał Żygowski>
--squashed into ba250cbdc63
* 0657df14a56 2024-03-14 mainboard/pcengines/apu2: Use variables instead of SMBIOS handle pointer <by Michał Żygowski>
* 892afaf9138 2024-03-13 src/mainboard/pcengines/apu2/vboot-rwa.fmd: Remove VPD regions <by Michał Żygowski>
--squashed into 7659e42c007
* 950c856f03d 2024-03-13 Apply suggestions from code review <by Michał Żygowski>
--squashed into 938b70dfe24
* 426b33d6e46 2024-03-12 src/mainboard/pcengines/apu2/mainboard.c: Measure PSP FW <by Michał Żygowski>
* 1c7cc9aba47 2024-03-11 src/southbridge/amd/pi/hudson/lpc.c: Use common AMD ACPI functions <by Michał Żygowski>
* 938b70dfe24 2024-03-11 sb/amd/pi/hudson: Fix programming LPC ROM registers <by Michał Żygowski>
--squashed with 950c856f03d
* 943e9d5d1a2 2024-03-07 mb/pcengines/apu2/vboot-rwa.fmd: Shrink WP_RO to 4MB to match SPI BP <by Michał Żygowski>
--squashed into 7659e42c007
* ba250cbdc63 2024-03-07 Makefile.inc: Put paylaod after fixed address files in CBFS <by Michał Żygowski>
--squashed with f7c2cc544b0
* 289dd47c5f0 2024-03-06 src/mainboard/pcengines/apu2: Add missing SMBIOS CPU and memory information <by Michał Żygowski>
* 7659e42c007 2024-03-06 src/mainboard/pcengines/apu2: Add vboot configuration and FMAP layout <by Michał Żygowski>
--squashed with 943e9d5d1a2 892afaf9138
* cffe6b2ba87 2024-03-06 src/vendorcode/amd/pi/Makefile.inc: Strip quotes from AGESA CBFS filename <by Michał Żygowski>
* 02404dee9e7 2024-03-06 src/southbridge/amd/pi/hudson: Move PSP FW to 0xfffa0000 <by Michał Żygowski>
* 39d5eb34040 2022-03-07 nb/amd/pi/00730F01/northbridge.c: enable PSP MMIO BARs <by Michał Żygowski>
* cf51738b267 2019-02-05 mb/apu2/romstage.c: force cold boot if ColdRstDet=1 <by Krystian Hebel>
* c4b0991c18b 2024-03-13 mb/apu2/romstage.c: zero CF9 before AGESA <by Sergii Dmytruk>
* 46b5f4c05a8 2018-10-01 mb/apu2/mainboard.c: enable ECC injection <by Krystian Hebel>
* db53b4958ea 2019-07-25 mb/apu2/mainboard.c: enable GENINT as GPIO <by Michał Żygowski>
* 86b73f7bc96 2017-01-01 pcengines/apu2: enable power on after power failure <by Kamil Wcislo>
* fcaaa3edc9a 2024-03-11 build.sh: add "apu{2,3,4,6}" commands <by Sergii Dmytruk>
* c15b2b2174c 2024-03-11 github/workflows/build.yml: build APU{2,3,4,6} boards <by Sergii Dmytruk>
* d8551060fda 2024-03-05 mb/apu2/mainboard.c: correct memory speed and size in SMBIOS Type 17 <by Sergii Dmytruk>
* 7d7065c92b4 2019-02-26 mb/apu2: add core boost runtime EFI option <by Michał Żygowski>
* 63e06c1ea2b 2019-12-31 mb/apu2: add watchdog runtime EFI options <by Krystian Hebel>
* 9a9a72bc352 2020-04-26 mb/apu2: add PCIe power management runtime EFI option <by Michał Żygowski>
* 4a1d4e184e9 2020-09-25 mb/pcengines/apu2: add APU6 variant <by Michał Żygowski>
* 82bb467e9fd 2024-03-01 security/vboot/Makefile.inc: fixup includes in $(CC_*) <by Sergii Dmytruk>
* 2b5d3081bc4 2022-09-16 mb/pcengines/apu2: changes required for SMMSTORE <by Krystian Hebel>
* 6b2b2e51966 2022-09-16 amd/pi/00730F01: make changes required to start SMM in TSEG <by Krystian Hebel>
* 02d8c1df0d1 2022-09-16 cpu/x86/lapic: use TSC in SMM <by Krystian Hebel>
* b02d5db42d0 2021-05-25 sb/amd/pi/hudson: use AMD common SPI block <by Michał Żygowski>
* e5df6ec2d18 2024-02-26 intel/Kconfig: allow enabling UDK_202005_BINDING for non-Intel <by Sergii Dmytruk>
* 4e714e14f9c 2024-02-26 vendorcode/dasharo/options.c: fix building for AMD <by Sergii Dmytruk>
--squashed into 8040bd2b891
* ca3c94d2770 2024-03-13 configs: Bump EDK2 to fix ESP scanning <by Michał Żygowski>
* 7749d39e919 2024-03-13 configs/config.protectli: Disable Firmware Update Mode <by Michał Żygowski>
* 82d3581c0d6 2024-03-12 configs: protectli: drop OC_WDT <by Maciej Pijanowski>
* af954531b5d 2024-03-06 confgs: enable EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS for protectli <by Maciej Pijanowski>
* 7d3647eca5b 2024-03-06 configs/config.protectli_vp2420: Soft disable ME <by Michał Żygowski>
* 587347b6b07 2024-03-01 configs/config.protectli_vp2420: Bump to v1.2.0 <by Michał Żygowski>
* 699e417ef86 2024-03-01 configs/config.protectli_vp46xx: Bump to v1.2.0 <by Michał Żygowski>
* 1b78e0d2b1e 2024-02-29 mb/clevo/tgl-u/Kconfig: enable secdata mocking <by Michał Kopeć>
* a2bf30dde1a 2024-02-29 mb/clevo/adl-p/Kconfig: enable secdata mocking <by Michał Kopeć>
* e39b415ae82 2024-02-27 configs/config.protectli_vp2410: bump ver to v1.1.0 <by Michał Kopeć>
* 5f551fe1af0 2024-02-19 configs/config.protectli_vp66xx: Enable redirection on 2nd UART <by Michał Żygowski>
* e77c362eeb9 2024-02-19 configs: Bump to revision supporting second serial port <by Michał Żygowski>
* 703bd6fdf25 2024-02-19 configs: Set proper options for the newest EDK2 revision <by Michał Żygowski>
* 2b52152e973 2024-02-19 configs: Bump edk2 to newest revision <by Michał Żygowski>
* cf9e269334d 2024-02-19 src/vendorcode/dasharo/options.c: Follow Kconfig if variables not enabled <by Michał Żygowski>
* 8e686826a19 2024-02-19 vendorcode/dasharo: Add Kconfig option to enable FUM flow <by Michał Żygowski>
* 483b0aecb6f 2024-02-15 superio/ite/it8659e/superio.c: Fix GPIO IO resources and masks <by Michał Żygowski>
* f470038cf18 2024-02-15 src/mainboard/protectli/vault_adl_p/devicetree.cb: Do not declare I/O for TPM <by Michał Żygowski>
* 085bf90e5db 2024-02-15 configs/config.protectli: Enable new features <by Michał Żygowski>
--squashed with 91e363d176b
* e1f314ebcf6 2024-02-15 mainboard/protectli/vault_adl_p: Enable VBOOT_ENABLE_CBFS_FALLBACK <by Michał Żygowski>
* 74ada09587d 2024-02-15 src/mainboard/protectli/vault_jsl/board.fmd: Add WP_RO region <by Michał Żygowski>
--squashed into f1a0f7e8c0d
* ffdb07176b8 2024-02-15 src/mainboard/protectli/vault_glk/board.fmd: Add WP_RO region <by Michał Żygowski>
--squashed into 4650292ce09
* 1e2c86d5f2d 2024-02-15 src/security/lockdown/Kconfig: allow WP_RO lock without vboot <by Michał Żygowski>
* 733aa5e3480 2024-02-15 soc/intel/jasperlake: Integrate OC WDT <by Michał Żygowski>
* e7832af58f1 2024-02-15 soc/intel/elkhartlake: Integrate OC WDT <by Michał Żygowski>
* ed1e766d5d1 2024-02-15 soc/intel/cannonlake: Integrate OC_WDT <by Michał Żygowski>
* 574a1979926 2024-02-14 mainboard/protectli/vault_jsl: Fix CRB TPM scope in devicetree <by Michał Żygowski>
--squashed into f1a0f7e8c0d
* dfe73c932e9 2024-02-23 configs/config.protectli_vp2420: bump to rc4 <by Michał Żygowski>
* 30d5f4f9450 2024-02-20 FUNDING.yml: add <by Maciej Pijanowski>
* e21ed0e40b8 2024-02-12 mainboard/msi: Add workarounds for building with CBFS greater than 16MiB <by Michał Żygowski>
* 602821df989 2024-02-12 src/cpu/intel/fit/Makefile.inc: Allow specifying FIT location <by Michał Żygowski>
* 408528de9f9 2024-02-12 src/soc/intel/alderlake/spi.c: Add PSF SPI destination for PCH-S <by Michał Żygowski>
* ad8df3294ef 2024-02-12 src/vendorcode/dasharo/Kconfig: Fix bug where unable to select HAP via IFDTOOl <by Michał Żygowski>
--squashed into c7d46b653b8
* e97b710e1f8 2024-02-12 mainboard/msi: Make the ROMHOLE be built into CBFS <by Michał Żygowski>
* 134cdfe56af 2024-02-12 util/msi: Allow to include ROMHOLE as CBFS file <by Michał Żygowski>
* e2cd499bd5e 2024-02-12 util/msi/romholetool: Add possibility to specify address and size manually <by Michał Żygowski>
--squash with bba3b758f5a
* 84c58a71976 2024-02-14 mainboard/protectli/vault_adl_p: Limit memory frequency to 4200MHz <by Michał Żygowski>
--in upstream, see e532725273b
* d0b56b80a93 2024-01-24 configs/config.protectli_vp66xx: Bump to v0.9.0-rc1 <by Michał Żygowski>
* 0694821d450 2024-01-16 .github/workflows/build.yml: Enable CI build for VP66XX <by Michał Żygowski>
* 89796469856 2024-01-22 src/soc/intel/alderlake/romstage/fsp_params.c: Add USB-C port enables <by Michał Żygowski>
* 876b308c862 2024-01-31 mainboard/protectli/vault_adl_p/gpio.c: Clean up macros and use correct settings <by Michał Żygowski>
* e532725273b 2024-01-31 mainboard/protectli/vault_adl_p/gpio.c: Remove comments and leave macros only <by Michał Żygowski>
* 81aea3dbab2 2024-01-12 src/mainboard/protectli/vault_adl_p: Add initial support <by Michał Żygowski>
--all 3 commits are in upstream:256e98f60471ed21067af4f91e986dccb619145e
some differences from our version done during review, took upstream version
this keeps `select VBOOT_NO_TPM` in Kconfig, is it needed?
* 63997adf769 2024-01-12 src/superio/ite/it8659e: Add driver <by Michał Żygowski>
--in upstream:
3f56bd2394d6992b26e2d893f15333590149abd0
1236b1c603c9ff020fe3d963b5b84085fdee6837
bfbc5cfcb2be562fc6fcf31dfcab9b648c9f81c7
* 569b851d93d 2024-01-24 src/superio/acpi: Add define to ignore the PNP active register <by Michał Żygowski>
* 08b6d8283a6 2024-01-12 util/superiotool/ite.c: Add support for ITE IT8659E <by Michał Żygowski>
* 2b6c8698a04 2024-02-09 src/vendorcode/dasharo/options.c: Fix build without SMMSTORE <by Michał Żygowski>
* c7d46b653b8 2024-02-06 vendorcode/dasharo: Add sleep type preference Kconfig option <by Michał Żygowski>
--squashed with ad8df3294ef
* 7274260269a 2024-02-06 configs/config.novacustom: Use public binaries from dasharo-blobs <by Michał Żygowski>
* 44c58724a0f 2024-02-06 configs/config.novacustom: Remove full configs <by Michał Żygowski>
* 24b5adc47cc 2024-02-13 util/ifdtool/ifdtool.c: Print current HAP state for all platforms <by Michał Żygowski>
* 9f637eba030 2024-01-30 util/ifdtool: Add complete set of HAP bit locations <by Michał Żygowski>
--affected by upstream:15a89ac7e8ca9377f98bd170c3a92a1fa241ded2 (formatting changes)
* 350aedcbb6c 2024-01-30 southbridge/intel/common/firmware: Allow to set HAP bit during build <by Michał Żygowski>
* aca7dc85c02 2023-12-13 configs/novacustom: remove -rc1 suffix from ver <by Michał Kopeć>
* c08eb3790ea 2023-12-11 ns50mu: set IccMax to the correct value <by Michał Kopeć>
--squashed into a09a521ded2
* 1202fa55a7f 2023-12-11 novacustom: adjust TCC to 80 degC <by Michał Kopeć>
* a09a521ded2 2023-12-08 clevo/tgl-u: configure VR params <by Michał Kopeć>
--squashed with c08eb3790ea
* 616add7c2ab 2023-12-08 clevo/adl-p/devicetree.cb: add VR configuration <by Michał Kopeć>
* ce33f351deb 2023-12-01 clevo/tgl-u: disable port reset <by Michał Kopeć>
--TODO: squash into 400a3dc4b5a?
* f0605923b9b 2023-12-01 mb/clevo/adl-p/devicetree.cb: acoustic / EMI noise mitigations <by Michał Kopeć>
* 25909a89022 2023-12-01 ns50mu: acoustic noise mitigations <by Michał Kopeć>
* 400a3dc4b5a 2023-12-01 clevo/tgl-u: enable port reset and disable USB OC <by Michał Kopeć>
* 6bb8cdf6a99 2023-12-01 clevo/{tgl-u, adl-p}: set ROM_I2C_EN high <by Michał Kopeć>
* b90efd45057 2023-11-30 nv40mz: unconfigure VNN_CTRL, V1P05_CTRL <by Michał Kopeć>
* 78260090f6d 2023-11-30 nv40mz: acoustic noise optimizations <by Michał Kopeć>
* 2498923da58 2023-11-23 mb/clevo/tgl-u,adl-p: Update CMOS checksum ranges <by Michał Żygowski>
* 98c9c0b8a1e 2023-11-17 src/ec/system76/ec/acpi/s76.asl: Change S76 device HID <by Michał Żygowski>
--obsoleted by upstream:aeb5ccd
* 5a94530fd4c 2023-11-17 Revert "configs/config.novacustom: Enable TBT SW Connection Manager" <by Michał Żygowski>
--cancelled out f2062784470
* 96283d04679 2023-11-17 src/soc/intel/alderlake/fsp_params.c: Select USB4 CM mode based on Kconfig <by Michał Żygowski>
* aacec059287 2023-11-17 configs/config.novacustom: Bump localversion <by Michał Żygowski>
* ca44bd185ae 2023-11-17 configs/config.novacustom: Bump EDK2 revision <by Michał Żygowski>
* ca472b82ea5 2023-11-16 src/soc/intel/tgl,adl/acpi: Change scope of power resources for S0IX <by Michał Żygowski>
--redone due to conflicts like this:
moved TBT0 and TBT1 into If (S0IX == 1)
moved TCON and TCOF out of If (S0IX == 1)
* ae005ae6247 2023-11-16 mb/clevo/tgl-u,adl-p/acpi/sleep.asl: Take TCSS out of D3cold on sleep <by Michał Żygowski>
* 152f55e6e72 2023-11-16 include/intelblocks/tcss.h: Change the values as per reference ocde <by Michał Żygowski>
* 5b12f78ace5 2023-11-13 system76/ec/acpi: add S0ix and display on/off hooks for PEP <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* 1057ea5351d 2023-11-14 configs/config.novacustom_nv4x_tgl: Remove redundant EDK2 network menu option <by Michał Żygowski>
--squash into 5951fc609b9
* f2062784470 2023-11-14 configs/config.novacustom: Enable TBT SW Connection Manager <by Michał Żygowski>
--cancelled out by 5a94530fd4c
* dc9b0471af4 2023-11-14 src/mb/clevo/{tgl-u/adl-p}/sleep.asl: do not call EC PTS and MWAK <by Michał Żygowski>
* 3cbcbc5d797 2023-11-14 src/mb/clevo: Avoid conflict of VBNV offset and ramtop in CMOS <by Michał Żygowski>
* 44e2ed9ecf9 2023-11-03 configs/config.novacustom*: add S3 disclaimer <by Michał Kopeć>
* 50bfac2e841 2024-02-06 mb/clevo/{tgl-u,adl-p}: Set FADT PM profile to mobile <by Michał Żygowski>
* e57d1f4004d 2024-01-30 src/mainboard/protectli/vault_jsl/bootblock.c: Fix the USB power control <by Michał Żygowski>
--squashed into f1a0f7e8c0d
* d73098bb545 2024-01-30 src/mainboard/protectli/vault_jsl/devicetree.cb: Fix the decode address <by Michał Żygowski>
--squashed into f1a0f7e8c0d
* bc7e5232d0e 2024-01-25 src/soc/intel/common/block/cse/cse.c: Fix reporting the HAP state <by Michał Żygowski>
--squashed into 2a5002e1c37
* fd2ee49e1b8 2024-01-23 configs/config.protectli_vp2410: Disable UEFI option backend and bump to rc5 <by Michał Żygowski>
* 9ae57e3cab6 2024-01-23 src/mainboard/protectli/vault_glk: Drop custom beep implementation <by Michał Żygowski>
* 20044edc52a 2024-01-23 src/soc/intel/apollolake/chip.c: Fix i8254 CLK gate settings logic <by Michał Żygowski>
--got reduced to a comment on some previous rebase
* 2a5002e1c37 2023-12-11 src/soc/intel/common/block/cse/cse.c: add info about HAP disabling <by Michał Żygowski>
--squashed with bc7e5232d0e
* 27d221b6ded 2023-12-07 dasharo/options.c: Read the ReBAR variable only once <by Michał Żygowski>
* 8040bd2b891 2023-12-06 inteblocks/cse,vendorcode/dasharo: Enable HMRFPO on FUM flow <by Michał Żygowski>
--squashed with 4e714e14f9c
* e2a8cdd9b85 2024-01-16 configs/config.protectli_vault_jsl: bump to v0.9.2 <by Michał Żygowski>
* c57196f999b 2024-01-11 configs/config.protectli_vp2410: bump to v1.1.0-rc4 <by Michał Żygowski>
* 33885afcb68 2024-01-11 soc/intel/apollolake/acpi/northbridge.asl: Declare missing memory regions <by Michał Żygowski>
* 9749669711d 2024-01-11 soc/intel/apollolake/acpi: Declare SMBUS device <by Michał Żygowski>
* a7f8742d13a 2024-01-11 soc/intel/apollolake: Disable DPTF if requested <by Michał Żygowski>
* 474250063c7 2024-01-05 configs/config.protectli_vp2410: Change order to options to fix build <by Michał Żygowski>
* 187b9775830 2024-01-04 .github/workflows/build.yml: Drop protectli-blobs repo and publish artifacts <by Michał Żygowski>
* 71a17ade340 2024-01-04 configs/config.protectli: Use blobs from dasharo-blobs repo <by Michał Żygowski>
* 4db09013174 2024-01-04 build.sh: Drop LAN ROM driver extraction <by Michał Żygowski>
* aee9ceee431 2024-01-04 configs: drop LAN ROM driver <by Michał Żygowski>
* 213dc9399c0 2024-01-04 payloads/external/iPXE/Makefile: Use iPXE from fork for i225 support <by Michał Żygowski>
* 1829692c124 2023-12-22 configs/config.protectli_vp2410: enable TPM PPI <by Michał Żygowski>
* 598401383cf 2023-12-21 src/mainboard/protectli/vault_glk/board.fmd: Add BOOTSPLASH region <by Michał Żygowski>
--squashed into 4650292ce09
* 8a220b02e09 2023-12-21 configs/config.protectli_vp2410: bump version to rc2 <by Michał Żygowski>
* 3014f18d3fe 2023-12-21 configs/config.protectli_vp2410: Disable coreboot MP init <by Michał Żygowski>
* dab41d06c03 2023-12-21 src/mainboard/protectli/vault_glk/devicetree.cb: add missing configuration <by Michał Żygowski>
--squashed into 4650292ce09
* 0b67afab2aa 2023-12-21 src/mainboard/protectli/vault_glk/bootblock.c: Cover SIO differences <by Michał Żygowski>
--squashed into 4650292ce09
* 21e52820f21 2023-12-18 configs/config.protectli_vp2410: add rc1 suffix to version <by Michał Żygowski>
* 805aeedb996 2023-12-18 Enable CI for Protectli VP2410 <by Michał Żygowski>
* 25a587bd50d 2023-12-18 src/mb/protectli/vault_ehl/acpi/superio.asl: Fix defines <by Michał Żygowski>
--squashed into 70c7895bd9a
* fa8b708faa5 2023-12-18 src/drivers/smmstore/store.c: Handle APL and GLK SMMSTORE alignment <by Michał Żygowski>
* 4650292ce09 2023-12-18 mb/protectli/vault_glk: Add VP2410 board support <by Michał Żygowski>
--squashed with 0b67afab2aa dab41d06c03 598401383cf ffdb07176b8 2c7c8c1e560
* 8d31ec12ef4 2023-12-18 src/soc/intel/apollolake/Kconfig: Enable SOC_INTEL_COMMON_BLOCK_HDA <by Michał Żygowski>
* 60b57c263e4 2021-03-11 src/soc/intel/apollolake/lpc.c: add legacy initialization <by Michał Żygowski>
* 270d37ab434 2021-05-06 src/soc/intel/apollolake/meminit_util_glk.c: add DRAM info for DDR4 <by Michał Żygowski>
* 5db4194be96 2021-03-11 src/soc/intel/apollolake/cpu.c: add missing CPU initialization <by Michał Żygowski>
* eaf305ade5c 2021-05-06 src/soc/intel/apollolake/cpu.c: report SMBIOS CPU frequencies <by Michał Żygowski>
* 45f0c2c448a 2021-03-11 src/soc/intel/apollolake/chip.c: add PCI CLKRUN and lockdown options <by Michał Żygowski>
* 92c91db12ff 2021-03-11 src/soc/intel/apollolake/chip.c: add IOAPIC and HPET parameters <by Michał Żygowski>
* 23891d19bfd 2021-04-21 src/soc/intel/apollolake/acpi/pci_irqs.asl: declare eSPI/LPC interrupt <by Michał Żygowski>
* 88275566a8b 2021-05-06 src/arch/x86/smbios.c: fix the SMBIOS CPU frequencies <by Michał Żygowski>
* bdfe0a8ac3c 2023-12-29 configs/config.protectli_vp2420: bump edk2 revision <by Michał Żygowski>
* 177b1285cd0 2023-12-19 configs/config.protectli_vp46xx: Update configs <by Michał Żygowski>
* d4cab30b3bb 2023-12-18 src/drivers/intel/fsp2_0/fsp_mpinit.c: Fix FSP MP init flow <by Michał Żygowski>
* 07952757b3c 2023-12-19 src/drivers/intel/fsp2_0/Makefile.inc: Fix typo <by Michał Żygowski>
* a6b3db1ec11 2023-12-15 configs/config.protectli_vault_jsl: bump to rc2 <by Michał Żygowski>
* cb3ea998213 2023-12-11 configs/config.protectli_cml_vp46xx: Disable OptionROMs by default <by Michał Żygowski>
* 42ae74a84b8 2023-12-08 configs/config.protectli_vault_jsl: Unify options with other boards <by Michał Żygowski>
* dd0551356fc 2023-12-08 src/mainboard/protectli/vault_jsl: Add beeps on boot and errors <by Michał Żygowski>
* 6615018a99e 2023-12-08 mb/protectli/vault_jsl/romstage.c: Update emmory configuration for V1410 <by Michał Żygowski>
--squashed into f1a0f7e8c0d
* cb7fd2af52e 2023-12-15 build.sh: Change tabs to spaces <by Michał Żygowski>
* 89f6878816e 2023-12-15 configs/config.protectli_vp2420: Add rc1 suffix <by Michał Żygowski>
* 5c6c5705813 2023-12-15 Add CI build for Protectli VP2420 <by Michał Żygowski>
* 01bd1396e43 2023-11-23 build.sh: Update JSL build params <by Michał Żygowski>
--squashed into e6a727c733f
* e66fb0abe97 2023-11-20 configs/config.protectli_vault_jsl: bump LOCALVERSION <by Michał Żygowski>
* e6a727c733f 2023-11-20 Add CI integration for Protectli JSL boards <by Michał Żygowski>
--squashed with 01bd1396e43
* f1a0f7e8c0d 2023-11-20 mb/protectli/vault_jsl: Add board support <by Michał Żygowski>
--squashed with 6615018a99e d73098bb545 e57d1f4004d 574a1979926 74ada09587d b225fd17d48 de18e90bb03
* 522c287c6d4 2023-06-20 src/soc/intel/jasperlake/bootblock/report_platform.c: report CPU model names <by Michał Żygowski>
* c5f4b252f0d 2023-07-18 src/soc/intel/jasperlake: handle GNA device based on devicetree <by Michał Żygowski>
--got simplified down to one line, because the reset was in upstream
* 69711374bb8 2023-07-18 src/soc/intel/jasperlake/acpi/pmc.asl: hide PMC <by Michał Żygowski>
* baca0f60147 2023-11-27 configs/config.msi: bump EDK2 revision <by Michał Żygowski>
* 351a07e4f64 2023-11-25 device/resource_allocator_v4.c: force 64bit limit for resource bigger than 4G <by Michał Żygowski>
* 179f84dcdb8 2023-11-25 configs/config.msi_ms7e06: Remove duplicated REBAR bits settings <by Michał Żygowski>
--squashed into c8adf4838fe
* ed1c9f3ce08 2023-11-24 src/mainboard/msi/ms7e06: Fix spacing in SMBIOS product name <by Michał Żygowski>
--TODO: partly squash into aa5a32e3009?
* c8adf4838fe 2023-11-20 configs/config.msi: Increase default ReBAR bits <by Michał Żygowski>
--squashed with 179f84dcdb8
* c499f51e5ab 2023-11-20 device/pci_device: Fix setting selected ReBAR <by Michał Żygowski>
* 9e357f48e1b 2023-10-31 configs/config.novacustom*: bump to .1 release <by Michał Kopeć>
* e0b86240316 2023-10-27 build.sh: revert persistent bootsplash <by Michał Kopeć>
--squashed into 0afeeca271c
* 086baca8e57 2023-10-27 Revert "configs/config.protectli*: use default bootsplash" <by Michał Kopeć>
--cancelled out 848e6d964fb
* 32543d6638a 2023-10-26 build.sh: add bootsplash to vp4 <by Michał Kopeć>
--squashed into 0afeeca271c
* e9e19d0597d 2023-10-26 build.sh: vp4: get version from defconfig <by Michał Kopeć>
--squashed into 0afeeca271c
* d45587f0e9a 2023-10-26 build.sh: add bootsplash after building <by Michał Kopeć>
--squashed into 0afeeca271c
* 848e6d964fb 2023-10-26 configs/config.protectli*: use default bootsplash <by Michał Kopeć>
--cancelled out by 086baca8e57
* 50115ed2047 2023-10-26 .github/workflows/build.yml: don't publish artifacts for vp4 <by Michał Kopeć>
--squashed into d9e33a06783
* fcecab10838 2023-10-26 configs/config.protectli*: use native MP init <by Michał Kopeć>
* 8ce9de0ad29 2023-10-26 .github/workflows/build.yml: publish artifacts for vp4 <by Michał Kopeć>
--squashed into d9e33a06783
* ceca8d26298 2023-10-26 .github/workflows/build.yml: build vp4 in env Protectli <by Michał Kopeć>
--squashed into d9e33a06783
* d3236ad2107 2023-10-26 .github/workflows/build.yml: run build.sh outside of cb-sdk <by Michał Kopeć>
--squashed into d9e33a06783
* 0afeeca271c 2023-10-26 build.sh: add vp46xx target <by Michał Kopeć>
--squashed with e0b86240316 d45587f0e9a e9e19d0597d 32543d6638a
* d9e33a06783 2023-10-26 .github/workflows/build.yml: add Protectli CI <by Michał Kopeć>
--squashed with d3236ad2107 ceca8d26298 8ce9de0ad29 50115ed2047 c5d2d952941
* 0d681eb6bb9 2023-10-26 configs/config.protectli*: update for rebased coreboot <by Michał Kopeć>
* a0dc6882c48 2023-09-04 src/soc/intel/cannonlake/fsp_params.c: do not enable MSR_IA32_DEBUG_INTERFACE <by Michał Żygowski>
* 6fcb0238810 2023-09-04 src/soc/intel/cannonlake/lockdown.c: lock the MSR_IA32_DEBUG_INTERFACE <by Michał Żygowski>
* f58c1d9bb1a 2023-09-02 soc/intel/{skylake,cannonlake}: fix SMRAM locking <by Michał Żygowski>
--in upstream
* f46a9a3f70e 2023-08-16 src/soc/intel/cannonlake/romstage/romstage.c: call TXT romstage init if TXT enabled <by Michał Żygowski>
* cb921bda9e0 2023-08-16 src/security/intel/txt/romstage.c: make romstage init work on SOC_INTEL platforms <by Michał Żygowski>
--squashed with 2fcbd18c847
* 857127eec4e 2023-08-10 security/intel/txt: check for TXT indices presence before SCHECK <by Michał Żygowski>
--squashed with 982f94aa551
* d58587c50f8 2023-08-10 security/tpm: Add TPM2 NV_ReadPublic command support <by Michał Żygowski>
--squashed with e1306a39230 982f94aa551
--affected by upstream:47e9e8cde1810ee9f249027b14ee9f82a7a52d84 (runtime TPM switch)
moved things around and renamed tlcl_nv_read_public() to tlcl2_nv_read_public()
changed return type to tpm_result_t
* 92661140500 2023-08-07 security/intel/txt: Restart APs after successful SCHECK <by Michał Żygowski>
* 0429d2fbcb0 2023-08-07 cpu/x86/mp_init: Add code to restart APs <by Michał Żygowski>
* 9c24936dc41 2023-08-07 soc/intel/cannonlake: Add SoC-specific settings for TXT <by Michał Żygowski>
* efd965d08db 2023-08-07 security/intel/txt: Handle TPM properly when vboot enabled <by Michał Żygowski>
* b9167cea4a0 2023-08-07 security/intel/txt: Add missing information and improve logging <by Michał Żygowski>
* 57f1cb444f8 2023-10-26 configs: add vault_cml configs with Dasharo changes <by Michał Kopeć>
--affected by upstream:c42e28f077cbf108085dff8d847a74d23782d703
configs/config.protectli_cml_vp46xx
updated commit title
* fc526adde2f 2023-10-25 src/soc/intel: Fix runtime setting of DMA protection <by Michał Żygowski>
--TODO: squash into 2cfb4f403b7?
* 7faba57d076 2023-10-25 .github/workflows/build.yml: Add jobs for MSI desktop builds <by Michał Żygowski>
* 9617a3c4770 2023-10-25 build.sh: Rework the script and add support for MSI builds <by Michał Żygowski>
* 1c238af19b5 2023-10-25 configs/config.msi: Bump LOCALVERSION <by Michał Żygowski>
* ca609f2cffa 2023-10-25 configs/config.msi: Bump EDK2 revision <by Michał Żygowski>
* 788756265a7 2023-10-25 configs/config.msi: Enabel RAM Disk support <by Michał Żygowski>
* 183a0b38838 2023-10-25 src/soc/intel/alderlake: Fix FSP params guarding for RaptorLake <by Michał Żygowski>
* 1410ad089af 2023-10-25 src/mainboard/msi: Enable HWP scalability tracking <by Michał Żygowski>
* 400967c16c7 2023-10-25 src/mainboard/msi: Select VBOOT_CLEAR_RECOVERY_EACH_BOOT <by Michał Żygowski>
* a08cf9dd264 2023-10-23 Add support for Raptor Lake-S Refresh <by Michał Żygowski>
* 95208944fd5 2023-10-23 src/mainboard/msi/ms7d25/smbios.c: Fix system product name <by Michał Żygowski>
--squashed into aa5a32e3009
* 1c065471446 2023-10-23 configs/config.msi: clean up configs and enable memory menu <by Michał Żygowski>
--affected by upstream:e68c6542fef9827913cff8d237006aeb1de45c0b (capsules)
affected by conflicts in a0dc25bb160
can't regenarate configs here, drops EDK2 stuff
--squashed into a0dc25bb160
* 766300c3d7b 2023-10-23 src/soc/intel/common/block/pcie/pcie_rp.c: Fix NULL pointer dereference <by Michał Żygowski>
--squashed with 535d6e9de82
--squashed into 792a65bf8ca
* a0dc25bb160 2023-10-23 configs: Update MSI boards configs <by Michał Żygowski>
--affected by upstream:e68c6542fef9827913cff8d237006aeb1de45c0b (capsules)
--squashed with 1c065471446
* 45014987f41 2023-10-23 mainboard/msi/{ms7d25,ms7e06}: Switch to RPL Client FSP <by Michał Żygowski>
* 8b4e5cf8bdd 2022-11-05 soc/intel/alderlake: Set PL1 Time to Intel default 56s for certain CPUs <by Michał Żygowski>
--affected by upstream:d6d83c19128f2605a604f23c3989d84784a3e7e0 (SKU list)
affected by upstream:c8d47169f43da95fcf8a8c385d49e0a464e58a97 (SKU list)
* f1faaa9ec9e 2023-08-25 soc/intel/alderlake: Move OC WDT to SOC directory and add RPL-S HID <by Michał Żygowski>
* b5578e02580 2023-09-04 src/soc/intel/alderlake/acpi.c: Fix reported C-states on desktop processors <by Michał Żygowski>
* 696b51febba 2023-09-23 mb/msi/ms{7d25,7e06}/romstage_fsp_params.c: set memory profile <by Sergii Dmytruk>
* 10d333ed3df 2023-01-30 soc/intel/alderlake: wire up SataPortsHotPlug FSP parameter <by Michał Kopeć>
* aa5a32e3009 2023-10-23 Add MSI MS7D25 and MS7306 boards <by Michał Żygowski>
--affected by upstream
affected by upstream:ce546192a2bf00759a8178e6dfb6cbb7a846b10c (number of jacks)
affected by upstream:c64bfdf23cbf4aaf41b47c401d0ca1865a95b50e (DIMM_SPD_SIZE)
--changed title to "Extend MSI MS7D25 and MS7E06 boards"
* 3d2047c9c6b 2023-09-22 src/mainboard/msi/ms7d25/devicetree.cb: Add fan control config <by Michał Żygowski>
* 278032dc26a 2023-09-22 src/mainboard/msi/ms7e06/devicetree.cb: Add fan control config <by Michał Żygowski>
* 3ed821cde64 2023-09-10 mb/msi/{ms7d25,ms7e06}/bootblock.c: Change the early SIO init to reflect vendor BIOS init <by Michał Żygowski>
* dfd56b1df56 2023-09-10 src/superio/nuvoton: Add HWM initialization code <by Michał Żygowski>
* 9610c53da41 2023-07-08 src/mainboard/msi/{ms7d25,ms7e06}/msi_id.S: update alignments and BPA <by Michał Żygowski>
--squashed into 57d63a016fb 4fad064a8c5
* 12287386511 2023-07-08 util/msi/romholetool: add structures present in newer MSI Z790 ROMs <by Michał Żygowski>
--squashed into bba3b758f5a
* c63136ff1aa 2023-07-06 src/mainboard/msi/ms7d25,ms7e06: ensure fmap_config.h is available for msi_id.S <by Michał Żygowski>
--squashed into 57d63a016fb 4fad064a8c5
* 57d63a016fb 2023-07-06 src/mainboard/msi/ms7e06: add MSI identification and ROMHOLE support <by Michał Żygowski>
--squashed with 9610c53da41 c63136ff1aa 30e69de844a 976486ae276
--changed title to "mb/msi/ms7e06: add MSI identification and ROMHOLE support"
* f7fb12b3726 2023-06-17 src/mainboard/msi/ms7d25/Kconfig: select to generate ROMHOLE <by Michał Żygowski>
--squashed into 4fad064a8c5
* ba94c881e6f 2023-06-17 src/mainboard/msi/Kconfig: add ROMHOLE option <by Michał Żygowski>
* bba3b758f5a 2023-06-17 util/msi: add utility to generate the MSI ROMHOLE <by Michał Żygowski>
--squashed with 12287386511 e2cd499bd5e
* 4fad064a8c5 2023-05-19 mb/msi/ms7d25: add board identification <by Michał Żygowski>
--squashed with 9610c53da41 f7fb12b3726 c63136ff1aa 30e69de844a 976486ae276
--changed title to "mb/msi/ms7d25: add MSI identification and ROMHOLE support"
* b01d85ad9ed 2023-10-25 configs/config.novacustom_nv4x_adl: Restore mistakenly removed EDK2 repo <by Michał Żygowski>
* 5dd91346889 2023-10-03 vendorcode/dasharo: add function to wipe options <by Michał Kopeć>
* 8043768088c 2023-10-13 configs: update EDK2 revision to configurable ME state <by Michał Żygowski>
* 52b3385247b 2023-10-12 src/vendorcode/dasharo/options.c: use default ME mode from Kconfig <by Michał Żygowski>
* 8fe1847cdf5 2023-10-12 include/intelblocks/me_15.h: Add EHL HAP definition <by Michał Żygowski>
--squashed into 2cfb4f403b7
* 4becd3f771e 2023-04-18 src/lib/cbfs.c: skip bootblock verification <by Michał Żygowski>
* e00e7ac1203 2023-09-28 drivers/generic/cbfs-{serial,uuid}: fallback to EFI var if CBFS file not found <by Michał Żygowski>
* 70c7895bd9a 2023-10-11 Add Protectli VP2420 Dasharo code <by Michał Żygowski>
--squashed with 25a587bd50d
* e71b31f458f 2023-10-10 configs/config.dell_optiplex_9010_sff_txt: remove blobs from config <by Michał Żygowski>
* 9acd528a74a 2023-10-03 configs/config.dell_optiplex_9010_sff: add USB SIGATT time <by Michał Żygowski>
* 061656236c6 2023-10-03 payloads/seabios: Add USB SIGATT time option <by Michał Żygowski>
* e0c6358d6d6 2023-10-03 configs/config.dell_optiplex_9010_sff_txt: add config for Intel TXT <by Michał Żygowski>
* a52d7fe585b 2023-10-03 src/northbridge/intel/sandybridge/Kconfig: set UDK binding to fix compilation <by Michał Żygowski>
* 13269b89634 2023-10-03 nb/sandybridge,sb/intel/common: Add ACPI support for PCIe PME and hotplug events <by Michał Żygowski>
* 1c3b7391dc3 2023-10-03 src/superio/smsc/sch5545/acpi/superio.asl: clear SIO PMEs properly <by Michał Żygowski>
* 58e24e4edb3 2023-09-14 payloads/external/iPXE: bump to 2023.8 <by Krystian Hebel>
* 4734bb3e519 2023-10-12 configs/config.novacustom*: enable EDK2 logging to cbmem <by Michał Kopeć>
* 3830f27bcff 2023-10-12 ec/system76/ec/acpi/ec.asl: remove cmos leftover <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* 384b01c3281 2023-10-12 ec/system76/ec/acpi/ec_ram.asl: remove fcmd leftovers <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* 345ac89779e 2023-10-12 src/soc/intel/tigerlake/acpi.c: Fix missing S0IX NVS init <by Michał Żygowski>
* e60a98db66d 2023-10-12 ec/s76/ec: completely remove KB backlight support <by Michał Kopeć>
--partially obsoleted by upstream:aeb5ccd
--squashed the rest into 1c9034a509c
* 80e839e30e1 2023-02-14 soc/intel/tigerlake/Kconfig: drop FSP notify <by Michał Kopeć>
* 505fc8ddeac 2023-02-14 soc/intel/tigerlake/lockdown.c: implement native PMC lockdown <by Michał Kopeć>
* 5dd62f4ea64 2023-10-11 configs/config.novacustom*: bump for battery threshold defaults <by Michał Kopeć>
* 3b8657f0f2e 2023-10-11 mb/clevo/tgl-u: enable S3 <by Michał Kopeć>
* 8fd0c4d17ef 2023-10-10 configs/config.novacustom_tgl: enable PS/2 skip detect in the EDK2 <by Michał Żygowski>
* 1c27979d643 2023-10-05 ec/system76/ec/acpi/ec.asl: enable kbled on wake <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* e420fd4cbae 2023-10-05 configs/config.novacustom: bump EDK2 for BAT thresholds defaults <by Michał Żygowski>
* b583b3fd136 2023-10-03 novacustom: remove Kconfig fragments <by Michał Kopeć>
* e7bb263c0ab 2023-10-03 configs/config.novacustom*: bump for serial console redir <by Michał Kopeć>
* b45db33d3a3 2023-10-03 configs/config.novacustom: remove unnecessary default settings <by Michał Żygowski>
--squashed into 9e6d076204a
* 7473097313f 2023-10-03 configs/config.novacustom*: disable network boot by default <by Michał Kopeć>
--squashed into 1c9034a509c
* e6de8f675f9 2023-10-03 soc/intel/alderlake/acpi/tcss.asl: hide ACPI IOM device <by Michał Kopeć>
* 9e6d076204a 2023-10-03 configs/config.novacustom*: bump edk2 for hotfixes <by Michał Kopeć>
--squashed with b45db33d3a3
--squashed into 63ebb58a8e7
* b5345d28ad6 2023-10-03 mb/clevo/adl-p/variants/nv40pz/hda_verb.c: do a reset of the codec <by Michał Kopeć>
--squashed into 1c9034a509c
* d5e3c6f3a2d 2023-10-03 mb/clevo/adl-p/devicetree.cb: enable audio codec <by Michał Kopeć>
* d47ffccfe9b 2023-10-02 hide cbtables, IOM, PMC ACPI devices <by Michał Kopeć>
* 3eea7fafca7 2023-10-02 src/ec/system76/ec/acpi/ec.asl: add touchpad toggle support <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* 63ebb58a8e7 2023-09-29 configs/config.novacustom: update configs <by Michał Żygowski>
--squashed with 9e6d076204a cb6648dd3f5
* cb6648dd3f5 2023-09-26 configs/config.novacustom*: bump edk2 for ESP scanning PCD <by Michał Kopeć>
--squashed into 63ebb58a8e7
* ead8b96b2cd 2023-09-26 configs/config.novacustom*tgl*: set version to v1.5.0 <by Michał Kopeć>
--squashed into aa7d8f85e95
* 5951fc609b9 2023-09-26 configs/config.novacustom*: enable Dasharo network menu <by Michał Kopeć>
--squashed with 1057ea5351d
* 8187cb4836e 2023-09-26 configs/config.novacustom*: enable power on ac by default in debug builds <by Michał Kopeć>
* 706cc9b53e7 2023-09-25 .github/workflows: fix incorrect build cmd <by Michał Kopeć>
--squashed into 3ae282c1b1c
* df2add235a5 2023-09-25 .github/workflows: skip make distclean <by Michał Kopeć>
--squashed into dea3fa2ee5d
* b8f2e0c1c4b 2023-09-25 .github/workflows: fix device matrix error <by Michał Kopeć>
--squashed into 3ae282c1b1c
* 4a2be826b0d 2023-09-25 .github/workflows: fix yaml syntax error <by Michał Kopeć>
--squashed into 3ae282c1b1c
* 3ae282c1b1c 2023-09-25 .github/workflows: generate debug and release builds <by Michał Kopeć>
--squashed with 706cc9b53e7, 4a2be826b0d, b8f2e0c1c4b
* 0fb8e3f5167 2023-09-25 .github/workflows: re-enable CI <by Michał Kopeć>
--squashed into dea3fa2ee5d
* 82f8e83f6b6 2023-09-25 configs/fragments/config.novacustom*: enable setup menu password <by Michał Kopeć>
--squashed into 1c9034a509c
* 68e6cf684ac 2023-09-25 configs/fragments/config.novacustom_release_build: add file <by Michał Kopeć>
* 0087c92ff41 2023-09-25 configs/fragments/config.novacustom_debug_build: add file <by Michał Kopeć>
* 55698535636 2023-09-25 configs/config.novacustom*adl*: set version number to v1.7.0 <by Michał Kopeć>
--squashed into aa7d8f85e95
* 9aae5118608 2023-09-25 configs/config.novacustom*: disable logging edk2 to cbmem <by Michał Kopeć>
--squashed into 1c9034a509c
* 86a4c57cf10 2023-09-25 configs/config.novacustom*: bump edk2 for ec console verbosity <by Michał Kopeć>
* fe07662fc83 2023-09-25 mb/clevo/tgl-u/ramstage.c: add missing include <by Michał Kopeć>
--squashed into 17e26bae3f3
* 6ee876832a0 2023-09-25 ec/s76: add bat threshold cmds <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* 8dadc6e42cd 2023-09-25 src/ec/system76/ec/commands.h: add missing option cmds <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* 36de4d5d038 2023-09-25 mb/clevo/tgl-u/variants/ns50mu/ramstage.c: add missing semicolon <by Michał Kopeć>
--squashed into 684b8b0795f
* e93fb13bccc 2023-09-25 ec/system76/ec/commands.h: add missing options definition <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* 1578c3a9c32 2023-09-25 mb/clevo/tgl-u/variants/nv40mz/ramstage.c: fix incorrect function definition <by Michał Kopeć>
--squashed into 684b8b0795f
* 8d1cd2db81e 2023-09-25 mb/clevo/tgl-u: fix incorrect radio option function call <by Michał Kopeć>
--squashed into 684b8b0795f
* b40f304ff09 2023-09-25 src/ec/system76/ec/commands.h: add missing SMFI CMD define <by Michał Kopeć>
--obsoleted by upstream:aeb5ccd
* 10b8d3ac5c1 2023-09-25 src/vendorcode/dasharo/options.c: fix typos <by Michał Kopeć>
--squashed into f37ba726bb0
* d3b3e5059d1 2023-09-25 Update src/vendorcode/dasharo/options.c <by Michał Żygowski>
--squashed into f37ba726bb0
* ac0584455e8 2023-09-22 configs/config.novacustom*: show battery options in edk2 <by Michał Kopeć>
--squashed into 1c9034a509c
* 684b8b0795f 2023-09-22 mb/clevo/tgl-u/variants: add radio option handling <by Michał Kopeć>
--squashed with 8d1cd2db81e, 1578c3a9c32, 36de4d5d038
* 17e26bae3f3 2023-09-22 mb/clevo/tgl-u/ramstage.c: add battery and Power on AC option handling <by Michał Kopeć>
--squashed with fe07662fc83
* 61305edb623 2023-09-22 mb/clevo/adl-p/ramstage.c: wire up power on AC option <by Michał Kopeć>
* d78ec4ef8a9 2023-09-22 mb/clevo/adl-p/ramstage.c: add battery and radio option handling <by Michał Kopeć>
* f37ba726bb0 2023-09-22 vendorcode/dasharo: add radio and battery config options <by Michał Kopeć>
--squashed with d3b3e5059d1 10b8d3ac5c1
* eee479ae6c5 2023-09-20 mb/clevo/adl-p/variants/ns50pu/data.vbt: enable dynamic CDClock <by Michał Kopeć>
* 9db359377ae 2023-09-19 mb/clevo/tgl-u: add backlight levels in line with adl-p <by Michał Kopeć>
--squashed into 9db359377ae
* 9a9f1385b33 2023-09-21 vendorcode/dasharo/Kconfig: set BIOS_VENDOR if GENERATE_SMBIOS_TABLES <by Michał Kopeć>
--squashed into 2cfb4f403b7
* acae00675c9 2023-09-20 src/mainboard/clevo: adl-p & tgl-u: removed unused symbol <by Mixss>
--squashed into 1c9034a509c
* ee509e3e99c 2023-09-20 .pre-commit-config.yaml: add comments <by Maciej Pijanowski>
--squashed into dc1a9af17e5
* d81fd8a0077 2023-09-20 gfx/nvidia/optimus/Makefile.inc: Add SPDX license header <by Maciej Pijanowski>
* 9c173cbd2d0 2023-09-20 mb/clevo/[cmd,tgl]: use detect flag for touchpad <by Maciej Pijanowski>
* 118aadd54d0 2023-09-20 mb/clevo: Add missing SPDX license headers <by Maciej Pijanowski>
* 326cd525377 2023-09-20 ec/system76: Add missing SPDX license headers <by Maciej Pijanowski>
--obsoleted by upstream:aeb5ccd
* dc1a9af17e5 2023-09-19 pre-commit: add configs <by Maciej Pijanowski>
--squashed with ee509e3e99c
* aa7d8f85e95 2023-09-15 configs/config.novacustom: update configs <by Michał Żygowski>
--squashed with ead8b96b2cd, 55698535636
--squashed into 1c9034a509c
* f7fead7d5f4 2023-09-15 .github/workflows/build.yml: Change branch name to build from <by Michał Żygowski>
--squashed into dea3fa2ee5d
* 9fd5d4019c0 2023-09-14 mb/clevo/tgl-u,adl-p: clear recovery reason on each boot via BS entry <by Michał Żygowski>
* ed2a8b6e49b 2023-09-14 vc/dasharo: move camera and fan curve options <by Michał Żygowski>
* 6ede7817339 2023-09-14 src/soc/intel/alderlake/chip.c: workaround incorrect ACPI names for PCIe endpoints <by Michał Żygowski>
--squashed with 535d6e9de82
* dea3fa2ee5d 2023-09-14 Add build script and CI <by Michał Żygowski>
--squashed with f7fead7d5f4 0fb8e3f5167 df2add235a5
* 1c9034a509c 2023-09-14 Add Novacustom laptops targets and modifications <by Michał Żygowski>
--affected by upstream:b1ae6ca7ef8b848e53577cb9da46c19d2d5886a8 (barely)
affected by upstream:a5705f701d5ee5318a8f6c75f3499ae0362ec4aa
--squashed with acae00675c9 e60a98db66d aa7d8f85e95 9db359377ae ac0584455e8 82f8e83f6b6 9aae5118608 7473097313f b5345d28ad6 1375f4f9025 540dd4f6d03 6cd77aa95a7 a1170e32b73 d4c28312d77
* 76722311b43 2023-09-14 src/ec/system76: Add Novacustom modifications <by Michał Żygowski>
--in upstream as aeb5ccd
replaced with 0673d0feecf, 0f78015f8e9
* 94ad70fb9dc 2023-09-14 src/drivers/gfx/nvidia/: add Nvidia Optimus driver <by Michał Żygowski>
--squashed with 326cd525377
* 2020d83ddae 2023-02-23 src/soc/intel/tigerlake/romstage: Enable DMA protection based on config <by Kacper Stojek>
* 53e4c0a9595 2023-09-14 soc/intel/alderlake/acpi/pcie_pch_s.asl: add INT routing for ADL-S PEG ports <by Michał Żygowski>
* 32a2943ffa2 2023-09-14 vd/dasharo,soc/intel: add sleep type option <by Michał Żygowski>
--affected by upstream:354a54ac84a934c1ee606d3f74dcd5a1f2606347
src/soc/intel/tigerlake/acpi/tcss.asl
Just replaced ifdef with If (S0IX == 1) shifting everything
* 59b11d202a7 2023-09-14 src/soc/intel/alderlake/fsp_params.c: Fix ADL-P PEG port interrupt <by Michał Żygowski>
--affected by upstream:542dd2e4e64c
src/soc/intel/alderlake/fsp_params.c
* 792a65bf8ca 2023-03-09 src/soc/intel/common/block/pcie/pcie_rp.c: disable downstream devices if bridge not present <by Michał Żygowski>
--squashed with 535d6e9de82, 766300c3d7b
* a9a3f73bff8 2023-09-14 src/acpi/acpigen.c: write _STA as a name filed if direct status given <by Michał Żygowski>
* 69e995bf46b 2023-09-14 src/lib/smbios.c: set Dasharo major and minor version in type0 <by Michał Żygowski>
* 5f49cbc0256 2023-08-29 src/drivers/efi/efivars.c: avoid overwriting rdev <by Michał Żygowski>
* 2cfb4f403b7 2023-09-13 src/vendorcode/dasharo: add Dasharo features <by Michał Żygowski>
--squashed with 9a9f1385b33 8fe1847cdf5 f269b7d8b60
* 31085821e17 2023-09-13 Move ReBar and lock options to vendorcode <by Michał Żygowski>
* f4c08da1470 2023-08-23 superio/nuvoton/nct6687d/superio.c: add EFI var for power on after fail <by Sergii Dmytruk>
* 50dff2dae5f 2023-08-30 soc/intel/common/block/pmc/pmclib.c: use EFI var for power on after fail <by Sergii Dmytruk>
* d3deb836eff 2022-08-18 Load UEFI Logo into CBMEM <by Michał Kopeć>
--squashed with a89d0e6783c
* a4398ccb8c5 2023-06-20 payloads/external/iPXE: clean the tree before checkout <by Michał Żygowski>
* 14e801c4b5e 2022-11-07 src/security/lockdown/lockdown.c: Move dasharo_system_features_guid under #if CONFIG(DRIVERS_EFI_VARIABLE_STORE) <by Stojek139808>
--squashed into 44fcf16fe19
* 44fcf16fe19 2022-06-01 security/lockdown/lockdown.c: control lock via EFI variable <by Sergii Dmytruk>
--squashed with 14e801c4b5e
* cdf97e5fd7c 2022-06-15 security/tpm/tspi/tspi.c: tspi_tpm_is_setup: take VBOOT_NO_TPM into account <by Michał Kopeć>
--squashed into 2569035b2a6
* e8fcda23285 2022-06-15 drivers/tpm: initialize TPM in ramstage if VBOOT_NO_TPM <by Michał Kopeć>
--squashed into 2569035b2a6
* 2569035b2a6 2022-06-15 security/vboot: add option to not use the TPM <by Michał Kopeć>
--squashed with e8fcda23285, cdf97e5fd7c
* f3b42aa890c 2021-12-08 version: include Dasharo version in the build <by Michał Żygowski>
* b773844483c 2021-12-08 util/genbuild_h/genbuild_h.sh: generate Dasharo version <by Michał Żygowski>
* a675ab2a3d4 2020-07-14 .gitmodules: Switch to absolute HTTPS links <by Michał Żygowski>
* 0a280ff747b 2024-02-29 lib/rtc: Fix off-by-one error in February day count in leap year (tag: 24.02.01) <by Michał Żygowski>
Below are things which might be worth checking because there were conflicts due to unrelated/similar/upstreamed commits. There were more conflicts, but the rest were less ambiguous.
@miczyg1
https://github.com/Dasharo/coreboot/commit/abd99f5bdc6 mb/protectli/vault_jsl/devicetree.cb: Enable SATA in M.2 slot
contradicts https://github.com/Dasharo/coreboot/commit/ff4c53da3a2? So M.2 is actually supported? https://github.com/Dasharo/coreboot/commit/ff4c53da3a2 mainboard/protectli/vault_jsl/devicetree.cb: Disable SATA The board does not support SATA disks. Despite the M.2 slots have the SATA lines, the silicon does not support the dynamic switching between SATA and PCIe. Disable the SATA controller to make Windows happy, as the straps are set for PCIe lanes.
https://github.com/Dasharo/coreboot/commit/876b308c862 mainboard/protectli/vault_adl_p/gpio.c: Clean up macros and use correct settings https://github.com/Dasharo/coreboot/commit/e532725273b mainboard/protectli/vault_adl_p/gpio.c: Remove comments and leave macros only https://github.com/Dasharo/coreboot/commit/81aea3dbab2 src/mainboard/protectli/vault_adl_p: Add initial support
All 3 commits are in https://github.com/coreboot/coreboot/commit/256e98f60471ed21067af4f91e986dccb619145e Some differences from our version done during review, took upstream version, but kept
select VBOOT_NO_TPMinKconfig, is it needed? See https://github.com/Dasharo/coreboot/commit/d44c922bf99010cacec14eb706920c530c6b0c73 for what's left after rebase.
https://github.com/Dasharo/coreboot/commit/d9f08f95e80 mb/protectli/vault_adl_n: Initial support for VP32XX series
Broken by https://github.com/coreboot/coreboot/commit/bfbc5cfcb2be562fc6fcf31dfcab9b648c9f81c7 Worth checking that I rewrote GPIO setup correctly: https://github.com/Dasharo/coreboot/commit/25e99343114edf02d6fa449cb73a2bf3b7f963af#diff-0e327309e45b49d559c5f99a650162fba20ca0b4302700da225dec3f550885d9
https://github.com/Dasharo/coreboot/commit/24906e70c23 src/soc/intel/alderlake/Kconfig: Deprecate ADL FSP
Needs verification because upstream changed sorting, conditions and formatting. New version: https://github.com/Dasharo/coreboot/commit/1e911ceaaf5e10a5e6f8fc0b90b303f1d7d89b96
https://github.com/Dasharo/coreboot/commit/f8d51ef980f mb/protectli/vault_adl_p/devicetree.cb: Assign CLKSRCs and enable ASPM
seems to be part of https://github.com/coreboot/coreboot/commit/256e98f60471ed21067af4f91e986dccb619145e Difference with upstream for
device ref pcie_rp10 on:
- our commit
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,- upstream (should stay like this?)
.flags = PCIE_RP_LTR | PCIE_RP_CLK_REQ_UNUSED,
https://github.com/Dasharo/coreboot/commit/ca472b82ea5 src/soc/intel/tgl,adl/acpi: Change scope of power resources for S0IX
Redone
src/soc/intel/tigerlake/acpi/tcss.asldue to conflicts like this:
- moved TBT0 and TBT1 into If (S0IX == 1)
- moved TCON and TCOF out of If (S0IX == 1)
https://github.com/Dasharo/coreboot/commit/4399b904b5310597d9dd77e24d8bd3f9a892ccd2#diff-da101acd428368e461e304b5fe2dd80f2976ba1b080c9c45ecd7eb3299c59e04
Odroid H4 (https://github.com/Dasharo/coreboot/commit/79a7b129838795cb3651c027c569b383e7ef44ea):
- Is it OK that
register "common_soc_config"is added at the top while also set fordevice ref i2c{0,1} on ... end? - There is also
const bool half_populated = true;inmainboard_memory_init_params()which was false in our version.
@mkopec
https://github.com/Dasharo/coreboot/commit/4f76d665f47 src/soc/intel/meteorlake/Kconfig: disable early SOL
Skipped, https://github.com/coreboot/coreboot/commit/dfa830e53092b4b52fa548c3616873a86c3818ad removed
config SOC_INTEL_METEORLAKE_SIGN_OF_LIFE. Needs adjusting condition onselect FSP_UGOP_EARLY_SIGN_OF_LIFE?
https://github.com/Dasharo/coreboot/commit/322cc5644bd lib/smbios.c: fill in BIOS characteristics depending on payload
Bug in the value of
BIOS_EXT2_CHARACTERISTICS_BIOS_BOOT?
https://github.com/Dasharo/coreboot/commit/c3f79301619 drivers/smmstore/ramstage.c: retry smmstore init up 5 times
Dropped because of https://github.com/coreboot/coreboot/commit/d57d5e3b3737607e4351ba460d0248a195279f2d, don't know if anything should break as a result.
https://github.com/Dasharo/coreboot/commit/1dbc6aabe7d mb/protectli/vault_cml: begin migration to 4.21
Is
- select HAVE_INTEL_PTTintentional? Correctly editedsrc/mainboard/protectli/vault_cml/devicetree.cbin https://github.com/Dasharo/coreboot/commit/fe86844bd318b1208335618d58fc7951b895e228?
https://github.com/Dasharo/coreboot/commit/9ff63111cae soc/intel/mtl: hook up public ucode
Skipped, upstream has https://github.com/coreboot/coreboot/commit/cfcb3620acd4187f143fc3b129dd21b2aa34f1d8. I think upstream version should work for us.
https://github.com/Dasharo/coreboot/commit/9cc779c8bce soc/intel/cmn/blk/oc_wdt: implement ACPI WDAT
https://github.com/coreboot/coreboot/commit/531c45e075c3 adds
acpi_soc_fill_wdat()unconditionally ifCONFIG_SOC_INTEL_COMMON_BLOCK_ACPIis set for TCO watchdog. So had to add#ifdefthere so it's not defined when OC watchdog is to be exposed via WDAT.
https://github.com/Dasharo/coreboot/commit/188a4127b68 soc/common/smbus: Support reading SPD5 hubs for DDR5 <by Jeremy Soller>
https://github.com/coreboot/coreboot/commit/60771bfdb102 caused conflict in
src/soc/intel/common/block/smbus/smbuslib.cResolved it and squashed with some later changes to get https://github.com/Dasharo/coreboot/commit/5b315aa is a result of squashing, but not entirely sure it's correct. affected by https://github.com/coreboot/coreboot/commit/e1306a39230 (smbus_read_spd() => spd_read())
ADL-P looks good. The pcie_rp10 got AER disabled because some Atheros WIFi cards caused a lot of errors in dmesg. @krystian-hebel found the cause, but we weren't able to fix this yet. Upstreamed the version with AER disabled, but for some reason we left it in our tree.
VBOOT_NO_TPM is still used AFAIK. It was added because vboot could cause entrance to recovery because of secdata. Even if the secdata was set to be mocked, vboot still could fail with some secdata error. Not sure if this is still valid.
ADL FSP sorting looks good. It is important for the IOT to go first.
WRT TCSS ACPI, there seem to be many changes so I'm not sure if this is correct or not.
Odroid H4. Half populated should be false. Redundant common_soc_config can be easily checked against the result in coreboot/build/mainbaord/static.c if al values are correctly assigned when only top common_soc_config is present, only i2c nested common_soc_config is present, and both are present.
ADL-P looks good. The pcie_rp10 got AER disabled because some Atheros WIFi cards caused a lot of errors in dmesg. @krystian-hebel found the cause, but we weren't able to fix this yet. Upstreamed the version with AER disabled, but for some reason we left it in our tree.
Ah, it is disabled on dasharo in https://github.com/Dasharo/coreboot/commit/78e2643a1dc2225d988affc68afa487bc37450a7, but the commit got automatically skipped as empty during rebase and I didn't check git log for the file until now.
WRT TCSS ACPI, there seem to be many changes so I'm not sure if this is correct or not.
Yeah, that's why I couldn't resolve that unintelligible conflict. It should be correct, because I first tried to recreate effect of the commit by replaying the changes on the version from its parent, verified that the file reached the same state and then did similar modifications to the version updated by the upstream.
Odroid H4. Half populated should be false.
Set it to false.
Redundant common_soc_config can be easily checked against the result in
coreboot/build/mainbaord/static.cif al values are correctly assigned when only top common_soc_config is present, only i2c nested common_soc_config is present, and both are present.
That's good to know. The syntax changes, but otherwise the result is the same. Top:
.common_soc_config = {
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
},
Bottom:
.common_soc_config.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
.common_soc_config.i2c[1] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
Not adding duplicated lines then and making commit shorter.
Latest CI: https://github.com/Dasharo/coreboot/actions/runs/13730715045
Updated a submodule and configs because PRs for EDK and dasharo-blobs were merged, also there were some new changes on dasharo which I incorporated.
@mkopec, @miczyg1, is thermal.asl needed there (https://github.com/Dasharo/coreboot/commit/ef411995534fa68974a471d0a640bf143ea66abd)? Nothing included it (#include "thermal.asl" added by me, might be wrong), so maybe it's not necessary?
I think we can drop that commit if nothing included it. The upstreamed Dasharo EC driver also doesn't have it
removed config SOC_INTEL_METEORLAKE_SIGN_OF_LIFE. Needs adjusting condition on select FSP_UGOP_EARLY_SIGN_OF_LIFE?
Ended up not working, can be dropped
lib/smbios.c: fill in BIOS characteristics depending on payload
Bug in the value of BIOS_EXT2_CHARACTERISTICS_BIOS_BOOT?
Of course, should be bit 1
drivers/smmstore/ramstage.c: retry smmstore init up 5 times
Dropped because of @.*** https://github.com/coreboot/coreboot/commit/d57d5e3b3737607e4351ba460d0248a195279f2d, don't know if anything should break as a result.
Yep, also abandoned upstream: https://review.coreboot.org/c/coreboot/+/73981
mb/protectli/vault_cml: begin migration to 4.21
Is - select HAVE_INTEL_PTT intentional? Correctly edited src/mainboard/protectli/vault_cml/devicetree.cb in
Was considered early on, but dropped later
soc/intel/mtl: hook up public ucode
Skipped, upstream has @.*** https://github.com/coreboot/coreboot/commit/cfcb3620acd4187f143fc3b129dd21b2aa34f1d8. I think upstream version should work for us.
👍
Updated the branch to incorporate feedback from above comments and pulled latest changes from dasharo.
I guess we need to start using dasharo-24.12 (rebased coreboot) or dasharo-24.12-edk202502 (rebased coreboot and EDK) for development, see if anything breaks and rename branches if there are no obvious issues.
Maybe we should we run qemu regression from https://github.com/Dasharo/open-source-firmware-validation against https://github.com/Dasharo/coreboot/tree/dasharo-24.12-edk202502 for starters?
Maybe we should we run qemu regression from https://github.com/Dasharo/open-source-firmware-validation against https://github.com/Dasharo/coreboot/tree/dasharo-24.12-edk202502 for starters?
Have those tests ever worked for QEMU? I get Flash firmware not implemented for platform config qemu at first, working around that makes it fail on various Rte ... keywords which I can define to reboot QEMU, then need to update qemu config. Tests at least run after that, but most are skipped or failed (e.g., EOFError: telnet connection closed or No match found for 'exit' in 3 minutes). main and develop produce similar results.
Yes, definitely at least when releasing it: https://docs.dasharo.com/variants/qemu_q35/releases/#v020-2024-06-26
I can take a look.
Some statistics as of today (2025-03-30):
- https://github.com/Dasharo/coreboot/compare/a1532790b90c714ab3e51555b68d4df1539ad72b...dasharo shows delta between upstream 24.12 and our fork
- we don't have a tag for upstream 24.12, should we add one?
- 640 commits with 651 changed files with 37,914 additions and 1,982 deletions
- average of 59 additions and 3 deletions per commit, which corresponds to medium size on gerrit
- Upstream-Status (
git log a1532790b90c..HEAD | grep "Upstream-Status" | sort | uniq -c):4 Upstream-Status: Backport [25.03] 1 Upstream-Status: Backport [584cdc99b70] 1 Upstream-Status: Backport [CB:84541] 1 Upstream-Status: Backport [CB:84542] 1 Upstream-Status: https://review.coreboot.org/c/coreboot/+/86750 1 Upstream-Status: Inappropriate (baseboard still in review) 2 Upstream-Status: Inappropriate (board still in review) 351 Upstream-Status: Inappropriate [Dasharo downstream] 1 Upstream-Status: Inappropriate [Dasharo downstream (most files)] 1 Upstream-Status: Partially Submitted [chain starting with CB:78809], 261 Upstream-Status: Pending 1 Upstream-Status: Submitted [CB:52731] 1 Upstream-Status: Submitted [CB:69217] 1 Upstream-Status: Submitted [CB:82039] 1 Upstream-Status: Submitted [CB:82696] 1 Upstream-Status: Submitted [CB:82697] 1 Upstream-Status: Submitted [cB:82731] 1 Upstream-Status: Submitted [CB:83385] 1 Upstream-Status: Submitted [CB:83424] 1 Upstream-Status: Submitted [CB:83425] 1 Upstream-Status: Submitted [CB:83426] 1 Upstream-Status: Submitted [CB:84926] 1 Upstream-Status: Submitted [CB:84927] 1 Upstream-Status: Submitted [CB:85278]- 355 (55.64%) inappropriate, 14 (2.19%) submitted (+1 partially, which gives 2.35%), 261 (40.91%) pending, 7 (1.10%) backports
- counting just upstreamable changes (submitted + pending), 15/276 = 5.43% submitted, 261/276 = 94.57% pending
- this sums up to 638, two topmost commits don't have
Upstream-Statustag, they probably weren't expected to be pushed as they enabled CI build for temporary branch and then reverted it - few inconsistencies in referencing upstream patches, one typo, those can be fixed on next rebase
- 355 (55.64%) inappropriate, 14 (2.19%) submitted (+1 partially, which gives 2.35%), 261 (40.91%) pending, 7 (1.10%) backports
Below are notable changes as a result of rebasing coreboot and EDK2 based on respective change logs (coreboot, EDK2) and list of EDK2's PRs to gather more information. coreboot's detailed changes are in 2610 commits so some changes might be missing here, but probably nothing really important.
There are obviously many more changes in upstream (including covered by change logs), but lots of them are code changes, lots are for unrelated architectures or boards (AARCH64, RISC-V, etc.) and some changes were upstreamed from Dasharo. EDK2 has also added dynamic generation of various ACPI tables (I believe we lack some of them like WSMT), but in Dasharo coreboot is chiefly responsible for it, so not mentioning those.
coreboot
Changed:
- running coreboot in 64-bit mode is now considered stable (we don't use it, but now we can give it a try)
EDK2
Added:
- handle "^" and "v"/"V" keys in pop-up forms (https://github.com/tianocore/edk2/pull/5788)
- support IAD-style USB input devices (https://github.com/tianocore/edk2/pull/6028)
Changed:
- enhance help in Delete Signature page (https://github.com/tianocore/edk2/pull/6528)
- default to TPM2.0 (https://github.com/tianocore/edk2/pull/6439)
- build proper SD/MMC boot descriptions (https://github.com/tianocore/edk2/pull/5839)
- fail the start of malfunctioning XHCI controllers (https://github.com/tianocore/edk2/pull/6033)
- measure ExitBootServices event on failure to exit boot services (https://github.com/tianocore/edk2/pull/6006)
Fixed:
- fixed a potential overflow on loading an EFI image (https://github.com/tianocore/edk2/pull/10617)
- fixed exponent unmarshaling when communicating with TPM2 (https://github.com/tianocore/edk2/pull/6086)
- fixed buffer overflow when dealing with device paths (https://github.com/tianocore/edk2/pull/3437)
- fixed buffer overflow when merging memory maps (https://github.com/tianocore/edk2/pull/6125)
- fixed descriptor misalignment in USB config handling (https://github.com/tianocore/edk2/pull/6442)
- fixed USB device not being reinitialized after a USB port reset (https://github.com/tianocore/edk2/pull/5794)
Hey, 24.12 TPM event log: both old coreboot custom format and upstreamed format seem to have bugs for TPM 1.2.
@marmarek opened an issue under Heads, but it seems that the stem of it is with cbmem -L output (it segfaults for upstreamed 1.2 format) as can be seen with logs at https://github.com/linuxboot/heads/issues/1956#issuecomment-2813314142
I tried to mitigate the issue reverting to old custom coreboot event log format, but it simply errlog to console Unknown TPM event log specification: as can be seen at https://github.com/linuxboot/heads/issues/1956#issuecomment-2813513116
Pretty sure you should face the issue with TPM 1.2 platforms with measured boot enabled? Is that a known issue?
Still valid until these are merged to upstream:
https://review.coreboot.org/c/coreboot/+/84926 https://review.coreboot.org/c/coreboot/+/84927