Avoiding slowdown of the circuit

[thesourcerer8]

This sounds a lot like you are adding a lot of delay into your design. It might make sense to calculate the critical path through the circuit first, and then apply this method only on all other pathes? (And only to apply as long as the modified pathes don't become the new critical path)

[Coloquinte]

You can (kind of) do this with the ll_explore command already, using -delay as an objective and picking a solution with zero additional delay. It's not yet possible from the logic_locking command, so I'm keeping this open until maybe I add it.

Note that the delay measure used is just the number of gates on the longest path: as far as I know there is not yet any timing analysis in Yosys.